decoder10to7.out

来自「verilog源码」· OUT 代码 · 共 27 行

Statistics for case statements in always block at line 49 in file
        'E:/EDA/Xilinx/active/projects/version2.14/calculat/DECODER10TO7.V'
===============================================
|           Line           |  full/ parallel  |
===============================================
|            52            |     no/auto      |
===============================================

Inferred memory devices in process 
	in routine decoder10to7 line 49 in file
         'E:/EDA/Xilinx/active/projects/version2.14/calculat/DECODER10TO7.V'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|       out_reg       |   Latch   |   7   |  Y  | N  | N  | N  | -  | -  | -  |
===============================================================================

out_reg (width 7)
-----------------
    reset/set: none


Warning: Latch inferred in design 'decoder10to7' read with
	'hdlin_check_no_latch'. (HDL-307)
Writing to hnl file 'E:\EDA\Xilinx\active\projects\version2.14\calculat\DPMCOMP.TMP/workdirs/WORK/decoder10to7.hnl'