selector.out

verilog源码

Inferred memory devices in process 
	in routine selector line 57 in file
         'E:/EDA/Xilinx/active/projects/version2.14/calculat/SELECTOR.V'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|  displaylower_reg   | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
|  displayupper_reg   | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

displaylower_reg (width 4)
--------------------------
    Async-reset: reset'


displayupper_reg (width 4)
--------------------------
    Async-reset: reset'


Writing to hnl file 'E:\EDA\Xilinx\active\projects\version2.14\calculat\DPMCOMP.TMP/workdirs/WORK/selector.hnl'