adder.out

来自「verilog源码」· OUT 代码 · 共 23 行

Inferred memory devices in process 
	in routine adder line 43 in file
         'E:/EDA/Xilinx/active/projects/version2.14/calculat/ADDER.V'.
===============================================================================
|    Register Name    |   Type    | Width | Bus | MB | AR | AS | SR | SS | ST |
===============================================================================
|      lower_reg      | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
|      upper_reg      | Flip-flop |   4   |  Y  | N  | Y  | N  | N  | N  | N  |
===============================================================================

lower_reg (width 4)
-------------------
    Async-reset: reset'


upper_reg (width 4)
-------------------
    Async-reset: reset'


Writing to hnl file 'E:\EDA\Xilinx\active\projects\version2.14\calculat\DPMCOMP.TMP/workdirs/WORK/adder.hnl'