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📄 dds.rpt

📁 本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子
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12 
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	N60.FBK.LFBK * N61.FBK.LFBK * "DOUT<1>".PIN
	+ "DATA<1>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * N60.FBK.LFBK * 
	N61.FBK.LFBK * "DOUT<1>".PIN * "DOUT<2>".PIN
;Imported pterms FB4_3
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * 
	N59.FBK.LFBK * N60.FBK.LFBK * N61.FBK.LFBK * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	N60.FBK.LFBK * N61.FBK.LFBK * "DOUT<2>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	N60.FBK.LFBK * N61.FBK.LFBK * "DOUT<1>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * N60.FBK.LFBK * 
	N61.FBK.LFBK * "DOUT<1>".PIN * "DOUT<2>".PIN * "DOUT<0>".PIN
    "DOUT<10>".CLKF  =  MCLK.PIN
    "DOUT<10>".RSTF  =  /RB
    "DOUT<10>".PRLD  =  GND    

/"DOUT<1>".T  =  /"DATA<0>" * /"DATA<1>"
	+ /"DATA<1>" * /N51.FBK.LFBK
	+ "DATA<0>" * "DATA<1>" * N51.FBK.LFBK
    "DOUT<1>".CLKF  =  MCLK.PIN
    "DOUT<1>".RSTF  =  /RB
    "DOUT<1>".PRLD  =  GND    

 "DOUT<2>".T  =  "DATA<2>" * /N51.FBK.LFBK * /N53.FBK.LFBK
	+ "DATA<0>" * "DATA<1>" * /"DATA<2>" * 
	N51.FBK.LFBK
	+ "DATA<0>" * /"DATA<2>" * N51.FBK.LFBK * 
	N53.FBK.LFBK
;Imported pterms FB2_13
	+ /"DATA<0>" * "DATA<2>" * /N53.FBK.LFBK
	+ /"DATA<1>" * "DATA<2>" * /N51.FBK.LFBK
	+ /"DATA<1>" * "DATA<2>" * /N53.FBK.LFBK
;Imported pterms FB2_15
	+ /"DATA<0>" * /"DATA<1>" * "DATA<2>"
	+ "DATA<1>" * /"DATA<2>" * N53.FBK.LFBK
    "DOUT<2>".CLKF  =  MCLK.PIN
    "DOUT<2>".RSTF  =  /RB
    "DOUT<2>".PRLD  =  GND    

 "DOUT<3>".T  =  "DATA<2>" * "DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * "DOUT<1>".PIN
	+ "DATA<1>" * "DOUT<1>".PIN * "DOUT<2>".PIN
;Imported pterms FB4_18
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	"DOUT<0>".PIN
	+ "DATA<0>" * "DATA<1>" * "DOUT<2>".PIN * 
	"DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * "DOUT<1>".PIN * 
	"DOUT<0>".PIN
	+ "DATA<0>" * "DOUT<1>".PIN * "DOUT<2>".PIN * 
	"DOUT<0>".PIN
    "DOUT<3>".CLKF  =  MCLK.PIN
    "DOUT<3>".RSTF  =  /RB
    "DOUT<3>".PRLD  =  GND    

 "DOUT<4>".T  =  "DATA<2>" * N55.FBK.LFBK * "DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	"DOUT<1>".PIN
	+ "DATA<1>" * N55.FBK.LFBK * "DOUT<1>".PIN * 
	"DOUT<2>".PIN
;Imported pterms FB4_14
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	"DOUT<1>".PIN * "DOUT<0>".PIN
;Imported pterms FB4_16
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	"DOUT<2>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * "DOUT<1>".PIN * 
	"DOUT<2>".PIN * "DOUT<0>".PIN
    "DOUT<4>".CLKF  =  MCLK.PIN
    "DOUT<4>".RSTF  =  /RB
    "DOUT<4>".PRLD  =  GND    

 "DOUT<5>".T  =  "DATA<2>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	"DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * "DOUT<1>".PIN
;Imported pterms FB4_13
	+ "DATA<1>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	"DOUT<1>".PIN * "DOUT<2>".PIN
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * N56.FBK.LFBK * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * "DOUT<2>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * "DOUT<1>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	"DOUT<1>".PIN * "DOUT<2>".PIN * "DOUT<0>".PIN
    "DOUT<5>".CLKF  =  MCLK.PIN
    "DOUT<5>".RSTF  =  /RB
    "DOUT<5>".PRLD  =  GND    

 "DOUT<6>".T  =  "DATA<2>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * "DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * "DOUT<1>".PIN
	+ "DATA<1>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * "DOUT<1>".PIN * "DOUT<2>".PIN
;Imported pterms FB4_12
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * N56.FBK.LFBK * N57.FBK.LFBK * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * "DOUT<2>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * "DOUT<1>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * "DOUT<1>".PIN * "DOUT<2>".PIN * "DOUT<0>".PIN
    "DOUT<6>".CLKF  =  MCLK.PIN
    "DOUT<6>".RSTF  =  /RB
    "DOUT<6>".PRLD  =  GND    

 "DOUT<7>".T  =  "DATA<2>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * "DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * "DOUT<1>".PIN
;Imported pterms FB4_10
	+ "DATA<1>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * "DOUT<1>".PIN * "DOUT<2>".PIN
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * 
	"DOUT<0>".PIN
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * "DOUT<2>".PIN * 
	"DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * "DOUT<1>".PIN * 
	"DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * "DOUT<1>".PIN * "DOUT<2>".PIN * 
	"DOUT<0>".PIN
    "DOUT<7>".CLKF  =  MCLK.PIN
    "DOUT<7>".RSTF  =  /RB
    "DOUT<7>".PRLD  =  GND    

 "DOUT<8>".T  =  "DATA<2>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * "DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	"DOUT<1>".PIN
	+ "DATA<1>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * "DOUT<1>".PIN * 
	"DOUT<2>".PIN
;Imported pterms FB4_7
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * 
	N59.FBK.LFBK * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	"DOUT<1>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * "DOUT<1>".PIN * 
	"DOUT<2>".PIN * "DOUT<0>".PIN
;Imported pterms FB4_9
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	"DOUT<2>".PIN * "DOUT<0>".PIN
    "DOUT<8>".CLKF  =  MCLK.PIN
    "DOUT<8>".RSTF  =  /RB
    "DOUT<8>".PRLD  =  GND    

 "DOUT<9>".T  =  "DATA<2>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * N60.FBK.LFBK * 
	"DOUT<2>".PIN
	+ "DATA<1>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	N60.FBK.LFBK * "DOUT<1>".PIN
	+ "DATA<1>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * N60.FBK.LFBK * 
	"DOUT<1>".PIN * "DOUT<2>".PIN
;Imported pterms FB4_4
	+ "DATA<0>" * "DATA<1>" * "DATA<2>" * 
	N55.FBK.LFBK * N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * 
	N59.FBK.LFBK * N60.FBK.LFBK * "DOUT<0>".PIN
	+ "DATA<0>" * "DATA<2>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	N60.FBK.LFBK * "DOUT<1>".PIN * "DOUT<0>".PIN
;Imported pterms FB4_6
	+ "DATA<0>" * "DATA<1>" * N55.FBK.LFBK * 
	N56.FBK.LFBK * N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * 
	N60.FBK.LFBK * "DOUT<2>".PIN * "DOUT<0>".PIN
	+ "DATA<0>" * N55.FBK.LFBK * N56.FBK.LFBK * 
	N57.FBK.LFBK * N58.FBK.LFBK * N59.FBK.LFBK * N60.FBK.LFBK * 
	"DOUT<1>".PIN * "DOUT<2>".PIN * "DOUT<0>".PIN
    "DOUT<9>".CLKF  =  MCLK.PIN
    "DOUT<9>".RSTF  =  /RB
    "DOUT<9>".PRLD  =  GND    

 MCLK.T  =  "U3/Q_0" * "U3/Q_1" * "U3/Q_2"
	+ "U3/Q_0" * /"U3/Q_1" * /"U3/Q_2" * /N62.FBK.LFBK
    MCLK.CLKF  =  CLK	;FCLK/GCK
    MCLK.SETF  =  /RB
    MCLK.PRLD  =  VCC    

 "U3/Q_0"  :=  /"U3/Q_0.FBK".LFBK
    "U3/Q_0".CLKF  =  CLK	;FCLK/GCK
    "U3/Q_0".RSTF  =  /RB
    "U3/Q_0".PRLD  =  GND    

/"U3/Q_1".T  =  /"U3/Q_0.FBK".LFBK
	+ /"U3/Q_1.FBK".LFBK * /"U3/Q_2.FBK".LFBK * /MCLK.PIN
    "U3/Q_1".CLKF  =  CLK	;FCLK/GCK
    "U3/Q_1".RSTF  =  /RB
    "U3/Q_1".PRLD  =  GND    

 "U3/Q_2".T  =  "U3/Q_0.FBK".LFBK * "U3/Q_1.FBK".LFBK
    "U3/Q_2".CLKF  =  CLK	;FCLK/GCK
    "U3/Q_2".RSTF  =  /RB
    "U3/Q_2".PRLD  =  GND    

****************************  Device Pin Out ****************************

Device : XC9572-7-PC44


                                  D     D  
                                  O     O  
                                  U     U  
                      M           T     T  
          C  T  T  T  C     T  T  <  V  <  
          L  I  I  I  L  R  I  I  2  C  1  
          K  E  E  E  K  B  E  E  >  C  >  
          --------------------------------  
         /6  5  4  3  2  1  44 43 42 41 40 \
    TIE | 7                             39 | DATA<2>
DATA<0> | 8                             38 | TIE
DATA<1> | 9                             37 | TIE
    GND | 10                            36 | TIE
    TIE | 11         XC9572-7-PC44      35 | DOUT<0>
    TIE | 12                            34 | DOUT<3>
    TIE | 13                            33 | DOUT<4>
    TIE | 14                            32 | VCC
    TDI | 15                            31 | GND
    TMS | 16                            30 | TDO
    TCK | 17                            29 | DOUT<5>
        \ 18 19 20 21 22 23 24 25 26 27 28 /
          --------------------------------  
          T  T  T  V  T  G  D  D  D  D  D  
          I  I  I  C  I  N  O  O  O  O  O  
          E  E  E  C  E  D  U  U  U  U  U  
                            T  T  T  T  T  
                            <  <  <  <  <  
                            1  9  8  7  6  
                            0  >  >  >  >  
                            >              


Legend :  NC  = Not Connected, unbonded pin
         TIE  = Tie pin to GND or board trace driven to valid logic level
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : XC9572-7-PC44
Use Timing Constraints                      : ON
Use Design Location Constraints             : ON
Create Programmable Ground Pins             : OFF
Use Advanced Fitting                        : ON
Use Local Feedback                          : ON
Use Pin Feedback                            : ON
Default Power Setting                       : STD
Default Output Slew Rate                    : FAST
Multi Level Logic Optimization              : ON
Timing Optimization                         : ON
Power/Slew Optimization                     : OFF
High Fitting Effort                         : ON
Automatic Wire-ANDing                       : ON
Xor Synthesis                               : ON
D/T Synthesis                               : ON
Use Boolean Minimization                    : ON
Global Clock(GCK) Optimization              : ON
Global Set/Reset(GSR) Optimization          : ON
Global Output Enable(GTS) Optimization      : ON
Collapsing pterm limit                      : 25
Collapsing input limit                      : 36
12

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