dds.v

本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子

module	DDS	( RB, CLK, DATA, DOUT, MCLK);
input		CLK,  RB;
input		[2:0]	DATA;
output		[10:0]	DOUT;
output		MCLK;
wire		[10:0]	SUM;
wire		DIV_CLK;

	FULLADDER     U1 (DATA, DOUT, SUM);
	R_SYDFF     U2 ( RB, SUM, DIV_CLK, DOUT);
	CNT10 	     U3 ( RB, CLK, DIV_CLK );
	assign MCLK = DIV_CLK ;

endmodule

/*	CNT10	*/
module	CNT10	( RESET_B, CLK, DIV_CLK );
input	RESET_B, CLK;
output  DIV_CLK;
reg	[3:0] Q;
	always	@( posedge CLK or negedge RESET_B)
		if ( !RESET_B )
			Q <= 0;
		else if ( Q == 9 )
			Q <= 0;
		else
			Q <= Q + 1;
	assign DIV_CLK = ~Q[3];
endmodule



/*	FULLADDER	*/
module	FULLADDER	(A, B, SUM);
input		[2:0]	A;
input		[10:0]	B;
wire		[9:0]	CY;
output		[10:0]	SUM;

	F_ADDER	FA00	(A[0], B[0],     0,   SUM[0], CY[0]);
  	F_ADDER	FA01	(A[1], B[1],  CY[0],  SUM[1], CY[1]);
 	F_ADDER	FA02	(A[2], B[2],  CY[1],  SUM[2], CY[2]);
 	F_ADDER	FA03	(     0, B[3],  CY[2],  SUM[3], CY[3]);
 	F_ADDER	FA04	(     0, B[4],  CY[3],  SUM[4], CY[4]);
 	F_ADDER	FA05	(     0, B[5],  CY[4],  SUM[5], CY[5]);
 	F_ADDER	FA06	(     0, B[6],  CY[5],  SUM[6], CY[6]);
 	F_ADDER	FA07	(     0, B[7],  CY[6],  SUM[7], CY[7]);
 	F_ADDER	FA08	(     0, B[8],  CY[7],  SUM[8], CY[8]);
 	F_ADDER	FA09	(     0, B[9],  CY[8],  SUM[9], CY[9]);
  	ADDER		FA10	(     0, B[10], CY[9], SUM[10]);
endmodule



/*	R_SYDFF	*/
module	R_SYDFF	( RB, D, CLK, Q);
input	RB, CLK;
input	[10:0] D;
output	[10:0] Q;
reg	[10:0] Q;
	always	@( posedge CLK or negedge RB )
		Q <= ( !RB )? 0: D;
endmodule


/*	F_ADDER	*/
module	F_ADDER	(A, B, CY_IN, SUM, CY_OUT);
input	A, B, CY_IN;
output	SUM, CY_OUT;
	assign   SUM  = A ^ B ^ CY_IN;
	assign   CY_OUT = (A & B) | (A & CY_IN) | (B & CY_IN);
endmodule 


/*	ADDER	*/
module	ADDER	(A, B, CY_IN, SUM);
input	A, B, CY_IN;
output	SUM;
	assign   SUM  = A ^ B ^ CY_IN;
endmodule