ch_counter.syr

本CD-ROM包括《Verilog-HDL实践与应用系统设计》一书中的全部例子

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : CH_COUNTER.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : CH_COUNTER
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : CH_COUNTER
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : CH_COUNTER.prj
Compiling included source file '../CNT100.v'
Module <CH_COUNTER> compiled.
Module <CNT100> compiled.
Module <COUNTER_SYNC> compiled.
Continuing compilation of source file 'CH_COUNTER.prj'
Compiling included source file 'd:/xilinx_webpack/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'CH_COUNTER.prj'
No errors in compilation
Analysis of file <CH_COUNTER.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing module <COUNTER_SYNC>.
Module <COUNTER_SYNC> is correct for synthesis.
 
Analyzing module <CNT100>.
Module <CNT100> is correct for synthesis.
 
Analyzing top module <CH_COUNTER>.
Module <CH_COUNTER> is correct for synthesis.

Synthesizing Unit <COUNTER_SYNC>.
    Related source file is ../CNT100.v.
    Found 24-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <COUNTER_SYNC> synthesized.


Synthesizing Unit <CNT100>.
    Related source file is ../CNT100.v.
    Found 7-bit up counter for signal <Q>.
    Summary:
	inferred   1 Counter(s).
Unit <CNT100> synthesized.


Synthesizing Unit <CH_COUNTER>.
    Related source file is ../CNT100.v.
Unit <CH_COUNTER> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Counters                         : 2
  24-bit up counter                : 1
  7-bit up counter                 : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <COUNTER_SYNC> ...

Optimizing unit <CNT100> ...

Optimizing unit <CH_COUNTER> ...

Merging netlists...

=========================================================================
Final Results
Output File Name                   : CH_COUNTER
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Xors                             : 29
  1-bit xor2                       : 29

Design Statistics
# Edif Instances                   : 155
# I/Os                             : 27

=========================================================================
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