lcd_control.v

使用Ｖeriolog hdl 编写手机屏测试程序．

module lcd_control(
                   clk,
                   lcd_enable,datain,
                   clkout,sd,hsy,vsy,data,oe,
                   get,power_ok,power_down,
                   v1,v2
              );
input clk;        //2.6MHz,大约为385ns
input lcd_enable;
input[17:0] datain;
output clkout,sd,hsy,vsy;
output[17:0] data;
output oe;
output get;
output power_ok;
output power_down;
output v1,v2;




reg clkout,sd,hsy,vsy;
reg[17:0] data;
reg [15:0] counter;
reg[7:0]   coun;     //power_down最后面2us的延时
reg     oe;      
reg     get;         //给传输模块的中断信号

reg[8:0]   counter_hsy;    //计算行的个数
reg[8:0]   counter_vsy;    //计算列的个数
reg[19:0]  delay_5ms;
reg[3:0]   counter_on;    
reg[2:0]   counter_down; 
reg        power_ok;
reg        power_down;
reg        v1,v2;
reg[2:0]   state;   


//暂时确定：0为什么都不做，1为初始化，2为power down，3为输出数据//
always@(posedge clk)
  begin
    case(state)


    3'b00://初始化
          begin
              clkout<=0;
              sd<=1;
              hsy<=0;
              vsy<=0;
              oe<=0;

              coun<=0;
              counter<=0;
              get<=0;
              counter_vsy<=0;
              counter_hsy<=0;
              delay_5ms<=0;
              counter_on<=0;
              counter_down<=0;
              power_ok<=0;
              power_down<=0;
              if(lcd_enable==1) state<=3'b01;
///////////////\\\\\\\\\\\\\\\/////
              v1<=1;
              v2<=1;
///////\\\\\\\\\\\\\\\\\\\\\\///////
          end

    3'b01://power on
          begin
               sd<=1;
///////////\\\\\\\\\\\///
               v1<=0;
               v2<=0;
//////////////\\\\\\\\\\\\\///// 
               if(delay_5ms==20'b1100101101110011010)      //ok                
                  begin   
                     state<=3'b010; 
                     delay_5ms<=0;
                  end
               else delay_5ms<=delay_5ms+1'b1;
          end

     3'b010:                //sd
          begin
                if(counter==16'b1111)
                    begin
                        clkout<=0;
                        counter<=0; 
                        if(counter_on==3'b110)  //ok
                            begin
                               state<=3'b011;
                               sd<=0;
                               counter_on<=0;
                            end
                        else    counter_on<=counter_on+1'b1;
                    end
                 else if(counter==16'b111)
                      begin 
                         counter<=counter+1'b1;
                         clkout<=1;
                         hsy<=1;
                         vsy<=1; 
                      end 
                 else  counter<=counter+1'b1;                      
         end

     3'b011:     //输出刷屏波形，但是不输出数据
           begin
                  oe<=0;                       
                  if(counter==16'b1111)
                      begin
                         clkout<=0;
                         counter<=0;
                         if(counter_hsy<=9'b1001)    ///010出3个hsy低
                             begin
                                hsy<=0;
                                counter_hsy<=counter_hsy+1'b1;
                             end
                         else if(counter_hsy<=9'b100010110)  ///100出 3个hsy高
                             begin
                                hsy<=1;
                                counter_hsy<=counter_hsy+1'b1;
                             end   
                         else  
                             begin
                                counter_hsy<=0;
                                counter_vsy<=counter_vsy+1'b1;
                             end

                         if(counter_vsy<=9'b01) vsy<=0;   //01出2个hsy的vsy低
                         else if(counter_vsy<=9'b101000101)  vsy<=1;  //101出4个hsy的vsy的高
                         else 
                            begin
                               vsy<=0;
                               counter_vsy<=0;
                               if(counter_on==4'b11) ///
                                  begin
                                     power_ok<=1;  
                                     state<=3'b110;
                                  end 
                               else counter_on<=counter_on+1'b1;
                            end                           
                    end
                 else if (counter==16'b111)
                    begin 
                        counter<=counter+1'b1;
                        clkout<=1;
                    end 
                 else  counter<=counter+1'b1;
          end


     3'b100:    //power down
          begin
             oe<=0;    //这个地方不要输出数据   
             sd<=1;                  
             if(counter==16'b1111)
                begin
                  clkout<=0;
                  counter<=0;
                  if(counter_hsy<=9'b1001)    
                       begin
                          hsy<=0;
                          counter_hsy<=counter_hsy+1'b1;
                       end
                  else if(counter_hsy<=9'b100010110)  
                       begin
                          hsy<=1;
                          counter_hsy<=counter_hsy+1'b1;
                       end   
                  else  
                       begin
                          counter_hsy<=0;
                          counter_vsy<=counter_vsy+1'b1;
                       end

                  if(counter_vsy<=9'b01) vsy<=0;
                  else if(counter_vsy<=9'b101000101)  vsy<=1;
                  else 
                       begin
                          vsy<=0;
                          counter_vsy<=0;
                          if(counter_down==3'b100) 
                             begin
                                state<=3'b101;
                                counter_down<=0;
                             end 
                          else counter_down<=counter_down+1'b1;
                       end                           
                 end
              else if (counter==16'b111)
                 begin 
                     counter<=counter+1'b1;
                     clkout<=1;
                 end 
              else  counter<=counter+1'b1;
          end

     3'b101:
          begin                      
              clkout<=0;
              hsy<=0;
              vsy<=0;
              if(coun==8'b11111111)      //延时2us
                  begin
                     power_down<=1;  //输出了就关了，通知输出模块换到默认状态 
                     sd<=1;
///////////////\\\\\\\\\\\\\\\/////
                     v1<=1;
                     v2<=1;
                     state<=3'b111;
                     coun<=0;
///////\\\\\\\\\\\\\\\\\\\\\\///////
                  end      
               else  coun<=coun+1'b1;                              
         end

    3'b111:
         begin
           if(coun==8'b010) 
             begin
                coun<=0;
                state<=0;
                power_down<=0;
             end
           else  coun<=coun+1'b1;
         end 
/////////////////////////////////////////////////////////////////
    3'b110:             //输出数据
      begin
        if(lcd_enable==1)
          begin 
             if(counter==16'b1111)
                begin
                  clkout<=0;
                  counter<=0;
                  if(counter_hsy<=9'b01001)    //01出2个hsy的低
                     begin
                        hsy<=0;
                        oe<=0;
                        counter_hsy<=counter_hsy+1'b1;
                     end
                   else if(counter_hsy<=9'b011101)   //011出2个hsy的高，oe低
                     begin
                         hsy<=1;
                         counter_hsy<=counter_hsy+1'b1;
                     end
                   else if(counter_hsy<=9'b100001101) //0111出4个hsy的oe高
                     begin
                         hsy<=1;                        
                         counter_hsy<=counter_hsy+1'b1;
                         if((counter_vsy<=9'b101000011)&(counter_vsy>9'b11)) //第5个到第6个hsy送数101《11
                            begin
                              data<=datain;
                              oe<=1;
                              get<=1; 
                            end
                     end     
                   else if(counter_hsy<=9'b100010110)//11个后面oe为高的hsy高
                      begin
                         oe<=0;
                         counter_hsy<=counter_hsy+1'b1;
                      end
                   else 
                       begin                        
                         counter_hsy<=0;
                         counter_vsy<=counter_vsy+1'b1;
                       end
 
                    if(counter_vsy<=9'b01) vsy<=0;   //2个hsy的vsy低电平
                    else if(counter_vsy<=9'b101000101)  vsy<=1;   //111总共出8个hsy的vsy周期
                    else 
                       begin
                         counter_vsy<=0; 
                         vsy<=0;
                       end
                end
             else if (counter==16'b111)
                   begin 
                      counter<=counter+1'b1;
                      clkout<=1;
                      get<=0;
                      power_ok<=0;
                   end 
             else  counter<=counter+1'b1;
         end
      else state<=3'b100;
     end
     endcase   //command


  end

endmodule