lpm_multtest.v

８＊８的乘法器verilog源代码,经过编译仿真的

`timescale 1ns/1ns 
module lpm_multest;
reg [7:0]dataa,datab,sum;
reg clock,clken,aclr;
wire[15:0] result;
parameter dely=25;
lpm_mult lpm_mult ( result, dataa, datab, sum, clock, clken, aclr ) ;

initial
begin
      clock=0;clken=0;aclr=0;sum=0;dataa=8'd0;datab=8'd0;
 #dely clock=1;dataa=8'd4;datab=8'd16;
 #dely clock=0;dataa=8'd2;datab=8'd4;
 #dely clock=1;dataa=8'd1;datab=8'd2;
 #dely clock=0;dataa=8'd4;datab=8'd5; 
 #dely clock=1;dataa=8'd8;datab=8'd2;
end
initial 
  begin
   $monitor($time,,,);
  end
endmodule