wave_gen_ver_s6.xise

32位单精度浮点加法器

<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->
  </header>

  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>

  <files>
    <file xil_pn:name="test_wave_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="tb_cmd_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
    </file>
    <file xil_pn:name="tb_fifo.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
    </file>
    <file xil_pn:name="tb_ram.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
    </file>
    <file xil_pn:name="tb_resetgen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="tb_resp_checker.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
    </file>
    <file xil_pn:name="tb_uart_driver.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="tb_uart_monitor.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
    </file>
    <file xil_pn:name="tb_wave_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
    </file>
    <file xil_pn:name="clk_div.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="clk_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="clkx_bus.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
    </file>
    <file xil_pn:name="cmd_parse.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
    </file>
    <file xil_pn:name="dac_spi.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
    </file>
    <file xil_pn:name="debouncer.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
    </file>
    <file xil_pn:name="lb_ctl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
    </file>
    <file xil_pn:name="meta_harden.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
    </file>
    <file xil_pn:name="out_ddr_flop.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
    </file>
    <file xil_pn:name="reset_bridge.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
    </file>
    <file xil_pn:name="resp_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
    </file>
    <file xil_pn:name="rst_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
    </file>
    <file xil_pn:name="samp_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
    </file>
    <file xil_pn:name="to_bcd.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
    </file>
    <file xil_pn:name="uart_baud_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
    </file>
    <file xil_pn:name="uart_rx.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
    </file>
    <file xil_pn:name="uart_rx_ctl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
    </file>
    <file xil_pn:name="uart_tx.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
    </file>
    <file xil_pn:name="uart_tx_ctl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
    </file>
    <file xil_pn:name="wave_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
    </file>
    <file xil_pn:name="wave_gen_pins.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
    </file>
    <file xil_pn:name="wave_gen_timing.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
    </file>
    <file xil_pn:name="ipcore_dir/char_fifo.xco" xil_pn:type="FILE_COREGEN">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
    </file>
    <file xil_pn:name="ipcore_dir/clk_core.xco" xil_pn:type="FILE_COREGEN">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
    </file>