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32位单精度浮点加法器

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wave_gen_ver_s6 is a top level Verilog type project of a programmable waveform 
	generator controlled via a PC (or other terminal device) using RS-232 serial 
	communication. 

DESIGN TYPE:
        ISE (chip 6SLX45t fgg484 -2)

PORTS 
Inputs:
          -- system signals
  * clk_pin			- System clock for the Wave_gen design.
  * rst_pin			- Resets the wave_gen design to initial state

          -- serial communications signals
  * rxd_pin			- Serial communications recieve input
  * lb_sel_pin		- Serial communications loop-back control pin


Outputs:          
          -- LED signals
  * led_pins 		-8-bit vector
            
          -- SPI related signals
  * spi_clk_pin		- SPI clock
  * SPI_MOSI_pin 	- SPI master-out-slave-in datum
  * DAC_cs_n_pin 	- DAC SPI chip select (active low)
  * DAC_clr_n_pin	- DAC clear
            
           -- serial communications signals
         
  * txd_pin			- Serial communications transmission signal
        

DESCRIPTION:
	The wave_gen design consists of several modular blocks:

* Clk_gen 	- Produces three clock signals: a x1 clock for the rx domain; 
				an xM/D clock (fx) for the tx domain; and a clk_samp which is 
				produced by dividing the tx clock by a selectable prescalar.
				
* rst_gen	- Provides reset signal to each of the three clock domains.

* lb_ctl 	- Provides a quick diagnostic capability by feeding the raw 
				serial rx signal back out the transmit line.
				
* uart_rx	- Captures serial data (rxd_pin buffered by an IBUF) and presents 
				it at the output of the module on the rx_data 8-bit bus.  The 
				signal rx_data_rdy pulses high for one clock when a new rx_data 
				is received. This data is then passed to the cmd_parse module.
				
* Cmd_parse	- Examines the incoming serial stream and executes commands based 
				on the contents.  The command parser always sends the received 
				character through the response generator and out the transmit path, 
				thus always echoing the received character. At the end of each 
				command either an