test_wave_gen_beh.prj

32位单精度浮点加法器

verilog work "ipcore_dir/char_fifo.v"
vhdl work "ipcore_dir/clk_core.vhd"
vhdl work "ipcore_dir/clk_core/example_design/clk_core_exdes.vhd"
verilog work "ipcore_dir/samp_ram.v"
verilog work "meta_harden.v"
verilog work "uart_tx_ctl.v"
verilog work "uart_rx_ctl.v"
verilog work "uart_baud_gen.v"
verilog work "to_bcd.v"
verilog work "reset_bridge.v"
verilog work "out_ddr_flop.v"
verilog work "debouncer.v"
verilog work "clk_div.v"
verilog work "uart_tx.v"
verilog work "uart_rx.v"
verilog work "samp_gen.v"
verilog work "rst_gen.v"
verilog work "resp_gen.v"
verilog work "lb_ctl.v"
verilog work "dac_spi.v"
verilog work "cmd_parse.v"
verilog work "clk_gen.v"
verilog work "clkx_bus.v"
verilog work "wave_gen.v"
verilog work "tb_uart_monitor.v"
verilog work "tb_uart_driver.v"
verilog work "tb_resp_checker.v"
verilog work "tb_resetgen.v"
verilog work "tb_ram.v"
verilog work "tb_fifo.v"
verilog work "tb_cmd_gen.v"
verilog work "tb_wave_gen.v"
verilog work "test_wave_gen.v"
verilog work "E:/xi14.2/14.2/ISE_DS/ISE//verilog/src/glbl.v"