📄 wave_gen_ver_s6.gise
字号:
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="wave_gen_ver_s6.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="ipcore_dir/char_fifo.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ipcore_dir/char_fifo.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="ipcore_dir/char_fifo.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ipcore_dir/char_fifo.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="ipcore_dir/clk_core.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ipcore_dir/clk_core.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="ipcore_dir/samp_ram.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="ipcore_dir/samp_ram.veo" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="ipcore_dir/samp_ram.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_wave_gen_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="test_wave_gen_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="test_wave_gen_isim_beh.wdb"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="test_wave_gen_stx_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1356269362" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="1051014138616327810" xil_pn:start_ts="1356269361">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356269417" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1356269417">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1356269418" xil_pn:in_ck="7919841228473433740" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1356269417">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="clk_div.v"/>
<outfile xil_pn:name="clk_gen.v"/>
<outfile xil_pn:name="clkx_bus.v"/>
<outfile xil_pn:name="clogb2.txt"/>
<outfile xil_pn:name="cmd_parse.v"/>
<outfile xil_pn:name="dac_spi.v"/>
<outfile xil_pn:name="debouncer.v"/>
<outfile xil_pn:name="lb_ctl.v"/>
<outfile xil_pn:name="meta_harden.v"/>
<outfile xil_pn:name="out_ddr_flop.v"/>
<outfile xil_pn:name="reset_bridge.v"/>
<outfile xil_pn:name="resp_gen.v"/>
<outfile xil_pn:name="rst_gen.v"/>
<outfile xil_pn:name="samp_gen.v"/>
<outfile xil_pn:name="tb_cmd_gen.v"/>
<outfile xil_pn:name="tb_fifo.v"/>
<outfile xil_pn:name="tb_ram.v"/>
<outfile xil_pn:name="tb_resetgen.v"/>
<outfile xil_pn:name="tb_resp_checker.v"/>
<outfile xil_pn:name="tb_uart_driver.v"/>
<outfile xil_pn:name="tb_uart_monitor.v"/>
<outfile xil_pn:name="tb_wave_gen.v"/>
<outfile xil_pn:name="test_wave_gen.v"/>
<outfile xil_pn:name="to_bcd.v"/>
<outfile xil_pn:name="uart_baud_gen.v"/>
<outfile xil_pn:name="uart_rx.v"/>
<outfile xil_pn:name="uart_rx_ctl.v"/>
<outfile xil_pn:name="uart_tx.v"/>
<outfile xil_pn:name="uart_tx_ctl.v"/>
<outfile xil_pn:name="wave_gen.v"/>
</transform>
<transform xil_pn:end_ts="1356269421" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="8727625949856083906" xil_pn:start_ts="1356269421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356269421" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="723214696143686528" xil_pn:start_ts="1356269421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356269421" xil_pn:in_ck="-4773031315194677944" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="2829982152511824995" xil_pn:start_ts="1356269421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/char_fifo.ngc"/>
<outfile xil_pn:name="ipcore_dir/char_fifo.v"/>
<outfile xil_pn:name="ipcore_dir/samp_ram.ngc"/>
<outfile xil_pn:name="ipcore_dir/samp_ram.v"/>
</transform>
<transform xil_pn:end_ts="1356269421" xil_pn:in_ck="-3584391731170706813" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1356269421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="clk_div.v"/>
<outfile xil_pn:name="clk_gen.v"/>
<outfile xil_pn:name="clkx_bus.v"/>
<outfile xil_pn:name="clogb2.txt"/>
<outfile xil_pn:name="cmd_parse.v"/>
<outfile xil_pn:name="dac_spi.v"/>
<outfile xil_pn:name="debouncer.v"/>
<outfile xil_pn:name="ipcore_dir/char_fifo.v"/>
<outfile xil_pn:name="ipcore_dir/samp_ram.v"/>
<outfile xil_pn:name="lb_ctl.v"/>
<outfile xil_pn:name="meta_harden.v"/>
<outfile xil_pn:name="out_ddr_flop.v"/>
<outfile xil_pn:name="reset_bridge.v"/>
<outfile xil_pn:name="resp_gen.v"/>
<outfile xil_pn:name="rst_gen.v"/>
<outfile xil_pn:name="samp_gen.v"/>
<outfile xil_pn:name="tb_cmd_gen.v"/>
<outfile xil_pn:name="tb_fifo.v"/>
<outfile xil_pn:name="tb_ram.v"/>
<outfile xil_pn:name="tb_resetgen.v"/>
<outfile xil_pn:name="tb_resp_checker.v"/>
<outfile xil_pn:name="tb_uart_driver.v"/>
<outfile xil_pn:name="tb_uart_monitor.v"/>
<outfile xil_pn:name="tb_wave_gen.v"/>
<outfile xil_pn:name="test_wave_gen.v"/>
<outfile xil_pn:name="to_bcd.v"/>
<outfile xil_pn:name="uart_baud_gen.v"/>
<outfile xil_pn:name="uart_rx.v"/>
<outfile xil_pn:name="uart_rx_ctl.v"/>
<outfile xil_pn:name="uart_tx.v"/>
<outfile xil_pn:name="uart_tx_ctl.v"/>
<outfile xil_pn:name="wave_gen.v"/>
</transform>
<transform xil_pn:end_ts="1356269467" xil_pn:in_ck="-3584391731170706813" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="4892012792230719730" xil_pn:start_ts="1356269421">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="test_wave_gen_beh.prj"/>
<outfile xil_pn:name="test_wave_gen_isim_beh.exe"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1356269468" xil_pn:in_ck="4867939620166161562" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="1371845337751116725" xil_pn:start_ts="1356269467">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="test_wave_gen_isim_beh.wdb"/>
</transform>
<transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -