📄 samp_ram.vho
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---------------------------------------------------------------------------------- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. ---- ---- This file contains confidential and proprietary information ---- of Xilinx, Inc. and is protected under U.S. and ---- international copyright and other intellectual property ---- laws. ---- ---- DISCLAIMER ---- This disclaimer is not a license and does not grant any ---- rights to the materials distributed herewith. Except as ---- otherwise provided in a valid license issued to you by ---- Xilinx, and to the maximum extent permitted by applicable ---- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND ---- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES ---- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING ---- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- ---- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and ---- (2) Xilinx shall not be liable (whether in contract or tort, ---- including negligence, or under any other theory of ---- liability) for any loss or damage of any kind or nature ---- related to, arising under or in connection with these ---- materials, including for any direct, or any indirect, ---- special, incidental, or consequential loss or damage ---- (including loss of data, profits, goodwill, or any type of ---- loss or damage suffered as a result of any action brought ---- by a third party) even if such damage or loss was ---- reasonably foreseeable or Xilinx had been advised of the ---- possibility of the same. ---- ---- CRITICAL APPLICATIONS ---- Xilinx products are not designed or intended to be fail- ---- safe, or for use in any application requiring fail-safe ---- performance, such as life-support or safety devices or ---- systems, Class III medical devices, nuclear facilities, ---- applications related to the deployment of airbags, or any ---- other applications that could lead to death, personal ---- injury, or severe property or environmental damage ---- (individually and collectively, "Critical ---- Applications"). Customer assumes the sole risk and ---- liability of any use of Xilinx products in Critical ---- Applications, subject only to applicable laws and ---- regulations governing limitations on product liability. ---- ---- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS ---- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------------------------------ The following code must appear in the VHDL architecture header:------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAGcomponent samp_ram port ( clka: in std_logic; wea: in std_logic_vector(0 downto 0); addra: in std_logic_vector(9 downto 0); dina: in std_logic_vector(15 downto 0); douta: out std_logic_vector(15 downto 0); clkb: in std_logic; web: in std_logic_vector(0 downto 0); addrb: in std_logic_vector(9 downto 0); dinb: in std_logic_vector(15 downto 0); doutb: out std_logic_vector(15 downto 0));end component;-- Synplicity black box declarationattribute syn_black_box : boolean;attribute syn_black_box of samp_ram: component is true;-- COMP_TAG_END ------ End COMPONENT Declaration -------------- The following code must appear in the VHDL architecture-- body. Substitute your own instance name and net names.------------- Begin Cut here for INSTANTIATION Template ----- INST_TAGyour_instance_name : samp_ram port map ( clka => clka, wea => wea, addra => addra, dina => dina, douta => douta, clkb => clkb, web => web, addrb => addrb, dinb => dinb, doutb => doutb);-- INST_TAG_END ------ End INSTANTIATION Template -------------- You must compile the wrapper file samp_ram.vhd when simulating-- the core, samp_ram. When compiling the wrapper file, be sure to-- reference the XilinxCoreLib VHDL simulation library. For detailed-- instructions, please refer to the "CORE Generator Help".⌨️ 快捷键说明
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