planahead_ise.tcl

32位单精度浮点加法器

# file: planAhead_ise.tcl
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set projDir [file dirname [info script]]
set projName clk_core
set topName clk_core_exdes
set device xc6slx45tfgg484-2

if {[file exists $projDir/$projName]} {
# if the project directory exists, delete it and create a new clean one
file delete -force $projDir/$projName
}

create_project $projName $projDir/$projName -part $device

set_property design_mode RTL [get_filesets sources_1]

## Source files
#set verilogSources [glob $srcDir/*.v]
import_files -fileset [get_filesets sources_1] -force -norecurse $projDir/../example_design/clk_core_exdes.v
import_files -fileset [get_filesets sources_1] -force -norecurse $projDir/../../clk_core.v


#UCF file
import_files -fileset [get_filesets constrs_1] -force -norecurse $projDir/../clk_core.ucf

set_property top $topName [get_property srcset [current_run]]

launch_runs -runs synth_1
wait_on_run synth_1

set_property add_step Bitgen [get_runs impl_1]
launch_runs -runs impl_1
wait_on_run impl_1