📄 clk_core.ejp

📁 32位单精度浮点加法器
💻 EJP
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Encore.Project.ProjectDir = C:/cases/13/040/wave_gen_ver_s6/ipcore_dir/tmp/_cgEncore.Project.ElaborationDir = C:/cases/13/040/wave_gen_ver_s6/ipcore_dir/tmp/_cgEncore.Project.TmpDir = C:/cases/13/040/wave_gen_ver_s6/ipcore_dir/tmp/_cgEncore.Project.Path = C:/cases/13/040/wave_gen_ver_s6/ipcore_dir/tmp/_cgEncore.Project.FlowVendor = Foundation_ISEEncore.Project.VhdlSim = trueEncore.Project.VerilogSim = trueEncore.Project.XDevice = xc6slx45tEncore.Project.XDeviceFamily = spartan6Encore.Project.XSpeedGrade = -2Encore.Project.XPackage = fgg484c_use_clkout1_bar = 0c_use_clkout2_bar = 0c_use_clkout3_bar = 0c_use_clkout4_bar = 0component_name = clk_corec_platform = ntc_use_freq_synth = 1c_use_phase_alignment = 1c_use_min_o_jitter = 0c_use_max_i_jitter = 0c_use_dyn_phase_shift = 0c_use_inclk_switchover = 0c_use_dyn_reconfig = 0c_use_spread_spectrum = 0c_primtype_sel = DCM_SPc_use_clk_valid = 0c_prim_in_freq = 27.000c_in_freq_units = Units_MHzc_secondary_in_freq = 100.000c_feedback_source = FDBK_AUTOc_prim_source = Single_ended_clock_capable_pinc_secondary_source = Single_ended_clock_capable_pinc_clkfb_in_signaling = SINGLEc_use_reset = 1c_use_locked = 1c_use_inclk_stopped = 0c_use_power_down = 0c_use_status = 0c_use_freeze = 0c_num_out_clks = 2c_clkout1_drives = BUFGc_clkout2_drives = No_bufferc_clkout3_drives = BUFGc_clkout4_drives = BUFGc_clkout5_drives = BUFGc_clkout6_drives = BUFGc_clkout7_drives = BUFGc_inclk_sum_row0 = Input Clock   Input Freq (MHz)   Input Jitter (UI)c_inclk_sum_row1 = primary          27.000            0.010c_inclk_sum_row2 = no secondary input clock c_outclk_sum_row0a = Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phasec_outclk_sum_row0b = Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)c_outclk_sum_row1 = CLK_OUT1    27.000      0.000      50.0      200.000     60.000c_outclk_sum_row2 = CLK_OUT2    27.000      0.000      50.0      940.740     60.000c_outclk_sum_row3 = no CLK_OUT3 output c_outclk_sum_row4 = no CLK_OUT4 outputc_outclk_sum_row5 = no CLK_OUT5 outputc_outclk_sum_row6 = no CLK_OUT6 outputc_outclk_sum_row7 = no CLK_OUT7 output c_clkout1_requested_out_freq = 27.000c_clkout2_requested_out_freq = 27c_clkout3_requested_out_freq = 100.000c_clkout4_requested_out_freq = 100.000c_clkout5_requested_out_freq = 100.000c_clkout6_requested_out_freq = 100.000c_clkout7_requested_out_freq = 100.000c_clkout1_requested_phase = 0.000c_clkout2_requested_phase = 0.000c_clkout3_requested_phase = 0.000c_clkout4_requested_phase = 0.000c_clkout5_requested_phase = 0.000c_clkout6_requested_phase = 0.000c_clkout7_requested_phase = 0.000c_clkout1_requested_duty_cycle = 50.000c_clkout2_requested_duty_cycle = 50.000c_clkout3_requested_duty_cycle = 50.000c_clkout4_requested_duty_cycle = 50.000c_clkout5_requested_duty_cycle = 50.000c_clkout6_requested_duty_cycle = 50.000c_clkout7_requested_duty_cycle = 50.000c_clkout1_out_freq = 27.000c_clkout2_out_freq = 27.000c_clkout3_out_freq = N/Ac_clkout4_out_freq = N/Ac_clkout5_out_freq = N/Ac_clkout6_out_freq = N/Ac_clkout7_out_freq = N/Ac_clkout1_phase = 0.000c_clkout2_phase = 0.000c_clkout3_phase = N/Ac_clkout4_phase = N/Ac_clkout5_phase = N/Ac_clkout6_phase = N/Ac_clkout7_phase = N/Ac_clkout1_duty_cycle = 50.0c_clkout2_duty_cycle = 50.0c_clkout3_duty_cycle = N/Ac_clkout4_duty_cycle = N/Ac_clkout5_duty_cycle = N/Ac_clkout6_duty_cycle = N/Ac_clkout7_duty_cycle = N/Ac_mmcm_notes = Nonec_mmcm_bandwidth = OPTIMIZEDc_mmcm_clkfbout_mult_f = 4.000c_mmcm_clkin1_period = 10.000c_mmcm_clkin2_period = 10.000c_mmcm_clkout4_cascade = FALSEc_mmcm_clock_hold = FALSEc_mmcm_compensation = ZHOLDc_mmcm_divclk_divide = 1c_mmcm_ref_jitter1 = 0.010c_mmcm_ref_jitter2 = 0.010c_mmcm_startup_wait = FALSEc_mmcm_clkout0_divide_f = 4.000c_mmcm_clkout1_divide = 1c_mmcm_clkout2_divide = 1c_mmcm_clkout3_divide = 1c_mmcm_clkout4_divide = 1c_mmcm_clkout5_divide = 1c_mmcm_clkout6_divide = 1c_mmcm_clkout0_duty_cycle = 0.500c_mmcm_clkout1_duty_cycle = 0.500c_mmcm_clkout2_duty_cycle = 0.500c_mmcm_clkout3_duty_cycle = 0.500c_mmcm_clkout4_duty_cycle = 0.500c_mmcm_clkout5_duty_cycle = 0.500c_mmcm_clkout6_duty_cycle = 0.500c_mmcm_clkfbout_phase = 0.000c_mmcm_clkout0_phase = 0.000c_mmcm_clkout1_phase = 0.000c_mmcm_clkout2_phase = 0.000c_mmcm_clkout3_phase = 0.000c_mmcm_clkout4_phase = 0.000c_mmcm_clkout5_phase = 0.000c_mmcm_clkout6_phase = 0.000c_mmcm_clkfbout_use_fine_ps = FALSEc_mmcm_clkout0_use_fine_ps = FALSEc_mmcm_clkout1_use_fine_ps = FALSEc_mmcm_clkout2_use_fine_ps = FALSEc_mmcm_clkout3_use_fine_ps = FALSEc_mmcm_clkout4_use_fine_ps = FALSEc_mmcm_clkout5_use_fine_ps = FALSEc_mmcm_clkout6_use_fine_ps = FALSEc_pll_notes = Nonec_pll_bandwidth = OPTIMIZEDc_pll_clk_feedback = CLKFBOUTc_pll_clkfbout_mult = 31c_pll_clkin_period = 37.037c_pll_compensation = SYSTEM_SYNCHRONOUSc_pll_divclk_divide = 1c_pll_ref_jitter = 0.010c_pll_clkout0_divide = 31c_pll_clkout1_divide = 32c_pll_clkout2_divide = 1c_pll_clkout3_divide = 1c_pll_clkout4_divide = 1c_pll_clkout5_divide = 1c_pll_clkout0_duty_cycle = 0.500c_pll_clkout1_duty_cycle = 0.500c_pll_clkout2_duty_cycle = 0.500c_pll_clkout3_duty_cycle = 0.500c_pll_clkout4_duty_cycle = 0.500c_pll_clkout5_duty_cycle = 0.500c_pll_clkfbout_phase = 0.000c_pll_clkout0_phase = 0.000c_pll_clkout1_phase = 0.000c_pll_clkout2_phase = 0.000c_pll_clkout3_phase = 0.000c_pll_clkout4_phase = 0.000c_pll_clkout5_phase = 0.000c_dcm_notes = Nonec_dcm_clkdv_divide = 2.000c_dcm_clkfx_divide = 2c_dcm_clkfx_multiply = 2c_dcm_clkin_divide_by_2 = FALSEc_dcm_clkin_period = 37.037c_dcm_clkout_phase_shift = NONEc_dcm_clk_feedback = 1Xc_dcm_clk_feedback_port = CLKOUT1c_dcm_deskew_adjust = SYSTEM_SYNCHRONOUSc_dcm_phase_shift = 0c_dcm_startup_wait = FALSEc_dcm_clk_out1_port = CLK0c_dcm_clk_out2_port = CLKFXc_dcm_clk_out3_port = NONEc_dcm_clk_out4_port = NONEc_dcm_clk_out5_port = NONEc_dcm_clk_out6_port = NONEc_dcm_clkgen_notes = Nonec_dcm_clkgen_clkfxdv_divide = 2c_dcm_clkgen_clkfx_divide = 1c_dcm_clkgen_clkfx_multiply = 4c_dcm_clkgen_dfs_bandwidth = OPTIMIZEDc_dcm_clkgen_prog_md_bandwidth = OPTIMIZEDc_dcm_clkgen_clkin_period = 10.000c_dcm_clkgen_clkfx_md_max = 4.000c_dcm_clkgen_spread_spectrum = NONEc_dcm_clkgen_startup_wait = FALSEc_dcm_clkgen_clk_out1_port = CLKFXc_dcm_clkgen_clk_out2_port = CLKFXc_dcm_clkgen_clk_out3_port = NONEc_clock_mgr_type = AUTOc_override_mmcm = 0c_override_pll = 0c_override_dcm = 1c_override_dcm_clkgen = 0c_dcm_pll_cascade = NONEc_primary_port = CLK_IN1c_secondary_port = CLK_IN2c_clk_out1_port = CLK_OUT1c_clk_out2_port = CLK_OUT2c_clk_out3_port = CLK_OUT3c_clk_out4_port = CLK_OUT4c_clk_out5_port = CLK_OUT5c_clk_out6_port = CLK_OUT6c_clk_out7_port = CLK_OUT7c_reset_port = RESETc_locked_port = LOCKEDc_clkfb_in_port = CLKFB_INc_clkfb_in_p_port = CLKFB_IN_Pc_clkfb_in_n_port = CLKFB_IN_Nc_clkfb_out_port = CLKFB_OUTc_clkfb_out_p_port = CLKFB_OUT_Pc_clkfb_out_n_port = CLKFB_OUT_Nc_power_down_port = POWER_DOWNc_daddr_port = DADDRc_dclk_port = DCLKc_drdy_port = DRDYc_dwe_port = DWEc_din_port = DINc_dout_port = DOUTc_den_port = DENc_psclk_port = PSCLKc_psen_port = PSENc_psincdec_port = PSINCDECc_psdone_port = PSDONEc_clk_valid_port = CLK_VALIDc_status_port = STATUSc_clk_in_sel_port = CLK_IN_SELc_input_clk_stopped_port = INPUT_CLK_STOPPEDc_clkin1_jitter_ps = 100.0c_clkin2_jitter_ps = 100.0ComponentName = clk_core
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