📄 clk_core.xise
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> <header> <!-- ISE source project file created by Project Navigator. --> <!-- --> <!-- This file contains project source information including a list of --> <!-- project source files, project and process properties. This file, --> <!-- along with the project source files, is sufficient to open and --> <!-- implement in ISE Project Navigator. --> <!-- --> <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> </header> <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/> <files> <file xil_pn:name="clk_core/clk_core.ucf" xil_pn:type="FILE_UCF"> <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="clk_core/example_design/clk_core_exdes.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> </file> <file xil_pn:name="clk_core.vhd" xil_pn:type="FILE_VHDL"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/> </file> </files> <properties> <property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/> <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|clk_core_exdes|xilinx" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top File" xil_pn:value="clk_core/example_design/clk_core_exdes.vhd" xil_pn:valueState="non-default"/> <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/clk_core_exdes" xil_pn:valueState="non-default"/> <property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> <property xil_pn:name="PROP_DesignName" xil_pn:value="clk_core" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-01-18T08:50:57" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="F8BC17D9D9FC4F8B9250CCD15D56A38C" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> </properties> <bindings/> <libraries/> <autoManagedFiles> <!-- The following files are identified by `include statements in verilog --> <!-- source files and are automatically managed by Project Navigator. --> <!-- --> <!-- Do not hand-edit this section, as it will be overwritten when the --> <!-- project is analyzed based on files automatically identified as --> <!-- include files. --> </autoManagedFiles></project>
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