float_add_modue_synthesis.v

32位单精度浮点加法器

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: P.28xd
//  \   \         Application: netgen
//  /   /         Filename: float_add_modue_synthesis.v
// /___/   /\     Timestamp: Sat Dec 22 23:30:45 2012
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -mhf -insert_glbl false -w -dir netgen/synthesis -ofmt verilog -sim float_add_modue.ngc float_add_modue_synthesis.v 
// Device	: xc7vx485t-2-ffg1761
// Input file	: float_add_modue.ngc
// Output file	: E:\kechengsheji\ha1\netgen\synthesis\float_add_modue_synthesis.v
// # of Modules	: 1
// Design Name	: float_add_modue
// Xilinx        : E:\xi14.2\14.2\ISE_DS\ISE\
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module float_add_modue (
  CLK, RSTn, Start_Sig, A, B, Result, Done_Sig, SQ_rA, SQ_rB, SQ_Temp, SQ_TempA, SQ_TempB, SQ_rExp, SQ_rExpDif
);
  input CLK;
  input RSTn;
  input Start_Sig;
  input [31 : 0] A;
  input [31 : 0] B;
  output [31 : 0] Result;
  output [3 : 0] Done_Sig;
  output [56 : 0] SQ_rA;
  output [56 : 0] SQ_rB;
  output [48 : 0] SQ_Temp;
  output [48 : 0] SQ_TempA;
  output [48 : 0] SQ_TempB;
  output [9 : 0] SQ_rExp;
  output [7 : 0] SQ_rExpDif;
  wire A_30_IBUF_0;
  wire A_29_IBUF_1;
  wire A_28_IBUF_2;
  wire A_27_IBUF_3;
  wire A_26_IBUF_4;
  wire A_25_IBUF_5;
  wire A_24_IBUF_6;
  wire A_23_IBUF_7;
  wire A_31_IBUF_8;
  wire A_22_IBUF_9;
  wire A_21_IBUF_10;
  wire A_20_IBUF_11;
  wire A_19_IBUF_12;
  wire A_18_IBUF_13;
  wire A_17_IBUF_14;
  wire A_16_IBUF_15;
  wire A_15_IBUF_16;
  wire A_14_IBUF_17;
  wire A_13_IBUF_18;
  wire A_12_IBUF_19;
  wire A_11_IBUF_20;
  wire A_10_IBUF_21;
  wire A_9_IBUF_22;
  wire A_8_IBUF_23;
  wire A_7_IBUF_24;
  wire A_6_IBUF_25;
  wire A_5_IBUF_26;
  wire A_4_IBUF_27;
  wire A_3_IBUF_28;
  wire A_2_IBUF_29;
  wire A_1_IBUF_30;
  wire A_0_IBUF_31;
  wire B_30_IBUF_32;
  wire B_29_IBUF_33;
  wire B_28_IBUF_34;
  wire B_27_IBUF_35;
  wire B_26_IBUF_36;
  wire B_25_IBUF_37;
  wire B_24_IBUF_38;
  wire B_23_IBUF_39;
  wire B_31_IBUF_40;
  wire B_22_IBUF_41;
  wire B_21_IBUF_42;
  wire B_20_IBUF_43;
  wire B_19_IBUF_44;
  wire B_18_IBUF_45;
  wire B_17_IBUF_46;
  wire B_16_IBUF_47;
  wire B_15_IBUF_48;
  wire B_14_IBUF_49;
  wire B_13_IBUF_50;
  wire B_12_IBUF_51;
  wire B_11_IBUF_52;
  wire B_10_IBUF_53;
  wire B_9_IBUF_54;
  wire B_8_IBUF_55;
  wire B_7_IBUF_56;
  wire B_6_IBUF_57;
  wire B_5_IBUF_58;
  wire B_4_IBUF_59;
  wire B_3_IBUF_60;
  wire B_2_IBUF_61;
  wire B_1_IBUF_62;
  wire B_0_IBUF_63;
  wire CLK_BUFGP_64;
  wire RSTn_IBUF_65;
  wire Start_Sig_IBUF_66;
  wire isOver_67;
  wire isUnder_68;
  wire isZero_69;
  wire isDone_70;
  wire \rA[56] ;
  wire \rA[55] ;
  wire \rA[54] ;
  wire \rA[53] ;
  wire \rA[52] ;
  wire \rA[51] ;
  wire \rA[50] ;
  wire \rA[49] ;
  wire \rA[48] ;
  wire SQ_rA_47_OBUF_80;
  wire \rA[46] ;
  wire \rA[45] ;
  wire \rA[44] ;
  wire \rA[43] ;
  wire \rA[42] ;
  wire \rA[41] ;
  wire \rA[40] ;
  wire \rA[39] ;
  wire \rA[38] ;
  wire \rA[37] ;
  wire \rA[36] ;
  wire \rA[35] ;
  wire \rA[34] ;
  wire \rA[33] ;
  wire \rA[32] ;
  wire \rA[31] ;
  wire \rA[30] ;
  wire \rA[29] ;
  wire \rA[28] ;
  wire \rA[27] ;
  wire \rA[26] ;
  wire \rA[25] ;
  wire \rA[24] ;
  wire \rA[23] ;
  wire \rA[22] ;
  wire \rA[21] ;
  wire \rA[20] ;
  wire \rA[19] ;
  wire \rA[18] ;
  wire \rA[17] ;
  wire \rA[16] ;
  wire \rA[15] ;
  wire \rA[14] ;
  wire \rA[13] ;
  wire \rA[12] ;
  wire \rA[11] ;
  wire \rA[10] ;
  wire \rA[9] ;
  wire \rA[8] ;
  wire \rA[7] ;
  wire \rA[6] ;
  wire \rA[5] ;
  wire \rA[4] ;
  wire \rA[3] ;
  wire \rA[2] ;
  wire \rA[1] ;
  wire \rA[0] ;
  wire \rB[56] ;
  wire \rB[55] ;
  wire \rB[54] ;
  wire \rB[53] ;
  wire \rB[52] ;
  wire \rB[51] ;
  wire \rB[50] ;
  wire \rB[49] ;
  wire \rB[48] ;
  wire \rB[46] ;
  wire \rB[45] ;
  wire \rB[44] ;
  wire \rB[43] ;
  wire \rB[42] ;
  wire \rB[41] ;
  wire \rB[40] ;
  wire \rB[39] ;
  wire \rB[38] ;
  wire \rB[37] ;
  wire \rB[36] ;
  wire \rB[35] ;
  wire \rB[34] ;
  wire \rB[33] ;
  wire \rB[32] ;
  wire \rB[31] ;
  wire \rB[30] ;
  wire \rB[29] ;
  wire \rB[28] ;
  wire \rB[27] ;
  wire \rB[26] ;
  wire \rB[25] ;
  wire \rB[24] ;
  wire \rB[23] ;
  wire \rB[22] ;
  wire \rB[21] ;
  wire \rB[20] ;
  wire \rB[19] ;
  wire \rB[18] ;
  wire \rB[17] ;
  wire \rB[16] ;
  wire \rB[15] ;
  wire \rB[14] ;
  wire \rB[13] ;
  wire \rB[12] ;
  wire \rB[11] ;
  wire \rB[10] ;
  wire \rB[9] ;
  wire \rB[8] ;
  wire \rB[7] ;
  wire \rB[6] ;
  wire \rB[5] ;
  wire \rB[4] ;
  wire \rB[3] ;
  wire \rB[2] ;
  wire \rB[1] ;
  wire \rB[0] ;
  wire isSign_380;
  wire \rExp[9]_rExp[9]_mux_119_OUT<9> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<8> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<7> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<6> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<5> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<4> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<3> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<2> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<1> ;
  wire \rExp[9]_rExp[9]_mux_119_OUT<0> ;
  wire \_n0739[0] ;
  wire \_n0739[1] ;
  wire \_n0739[2] ;
  wire \_n0739[3] ;
  wire \_n0739[4] ;
  wire \_n0739[5] ;
  wire \_n0739[6] ;
  wire \_n0739[7] ;
  wire \_n0739[8] ;
  wire \_n0739[10] ;
  wire \_n0739[11] ;
  wire \_n0739[12] ;
  wire \_n0739[13] ;
  wire \_n0739[14] ;
  wire \_n0739[15] ;
  wire \_n0739[16] ;
  wire \_n0739[17] ;
  wire \_n0739[18] ;
  wire \_n0739[19] ;
  wire \_n0739[20] ;
  wire \_n0739[21] ;
  wire \_n0739[22] ;
  wire \_n0739[23] ;
  wire \_n0739[24] ;
  wire \_n0739[25] ;
  wire \_n0739[26] ;
  wire \_n0739[27] ;
  wire \_n0739[28] ;
  wire \_n0739[29] ;
  wire \_n0739[30] ;
  wire \_n0739[31] ;
  wire \_n0739[32] ;
  wire \_n0739[33] ;
  wire \_n0739[34] ;
  wire \_n0739[35] ;
  wire \_n0739[36] ;
  wire \_n0739[37] ;
  wire \_n0739[38] ;
  wire \_n0739[39] ;
  wire \_n0739[40] ;
  wire \_n0739[41] ;
  wire \_n0739[42] ;
  wire \_n0739[43] ;
  wire \_n0739[44] ;
  wire \_n0739[45] ;
  wire \_n0739[46] ;
  wire \_n0739[47] ;
  wire \_n0739[48] ;
  wire \_n0739[49] ;
  wire \_n0739[50] ;
  wire \_n0739[51] ;
  wire \_n0739[52] ;
  wire \_n0739[53] ;
  wire \_n0739[54] ;
  wire \_n0739[55] ;
  wire \_n0739[56] ;
  wire \_n0759[0] ;
  wire \_n0759[1] ;
  wire \_n0759[2] ;
  wire \_n0759[3] ;
  wire \_n0759[4] ;
  wire \_n0759[5] ;
  wire \_n0759[6] ;
  wire \_n0759[7] ;
  wire \_n0759[8] ;
  wire \_n0759[10] ;
  wire \_n0759[11] ;
  wire \_n0759[12] ;
  wire \_n0759[13] ;
  wire \_n0759[14] ;
  wire \_n0759[15] ;
  wire \_n0759[16] ;
  wire \_n0759[17] ;
  wire \_n0759[18] ;
  wire \_n0759[19] ;
  wire \_n0759[20] ;
  wire \_n0759[21] ;
  wire \_n0759[22] ;
  wire \_n0759[23] ;
  wire \_n0759[24] ;
  wire \_n0759[25] ;
  wire \_n0759[26] ;
  wire \_n0759[27] ;
  wire \_n0759[28] ;
  wire \_n0759[29] ;
  wire \_n0759[30] ;
  wire \_n0759[31] ;
  wire \_n0759[32] ;
  wire \_n0759[33] ;
  wire \_n0759[34] ;
  wire \_n0759[35] ;
  wire \_n0759[36] ;
  wire \_n0759[37] ;
  wire \_n0759[38] ;
  wire \_n0759[39] ;
  wire \_n0759[40] ;
  wire \_n0759[41] ;
  wire \_n0759[42] ;
  wire \_n0759[43] ;
  wire \_n0759[44] ;
  wire \_n0759[45] ;
  wire \_n0759[46] ;
  wire \_n0759[47] ;
  wire \_n0759[48] ;
  wire \_n0759[49] ;
  wire \_n0759[50] ;
  wire \_n0759[51] ;
  wire \_n0759[52] ;
  wire \_n0759[53] ;
  wire \_n0759[54] ;
  wire \_n0759[55] ;
  wire \_n0759[56] ;
  wire \rA[47]_rA[47]_MUX_457_o ;
  wire \rA[46]_rA[47]_MUX_458_o ;
  wire \rA[45]_rA[47]_MUX_459_o ;
  wire \rA[44]_rA[47]_MUX_460_o ;
  wire \rA[43]_rA[47]_MUX_461_o ;
  wire \rA[42]_rA[47]_MUX_462_o ;
  wire \rA[41]_rA[47]_MUX_463_o ;
  wire \rA[40]_rA[47]_MUX_464_o ;
  wire \rA[39]_rA[47]_MUX_465_o ;
  wire \rA[38]_rA[47]_MUX_466_o ;
  wire \rA[37]_rA[47]_MUX_467_o ;
  wire \rA[36]_rA[47]_MUX_468_o ;
  wire \rA[35]_rA[47]_MUX_469_o ;
  wire \rA[34]_rA[47]_MUX_470_o ;
  wire \rA[33]_rA[47]_MUX_471_o ;
  wire \rA[32]_rA[47]_MUX_472_o ;
  wire \rA[31]_rA[47]_MUX_473_o ;
  wire \rA[30]_rA[47]_MUX_474_o ;
  wire \rA[29]_rA[47]_MUX_475_o ;
  wire \rA[28]_rA[47]_MUX_476_o ;
  wire \rA[27]_rA[47]_MUX_477_o ;
  wire \rA[26]_rA[47]_MUX_478_o ;
  wire \rA[25]_rA[47]_MUX_479_o ;
  wire \rA[24]_rA[47]_MUX_480_o ;
  wire \rA[23]_rA[47]_MUX_481_o ;
  wire \rA[22]_rA[47]_MUX_482_o ;
  wire \rA[21]_rA[47]_MUX_483_o ;
  wire \rA[20]_rA[47]_MUX_484_o ;
  wire \rA[19]_rA[47]_MUX_485_o ;
  wire \rA[18]_rA[47]_MUX_486_o ;
  wire \rA[17]_rA[47]_MUX_487_o ;
  wire \rA[16]_rA[47]_MUX_488_o ;
  wire \rA[15]_rA[47]_MUX_489_o ;
  wire \rA[14]_rA[47]_MUX_490_o ;
  wire \rA[13]_rA[47]_MUX_491_o ;
  wire \rA[12]_rA[47]_MUX_492_o ;
  wire \rA[11]_rA[47]_MUX_493_o ;
  wire \rA[10]_rA[47]_MUX_494_o ;
  wire \rA[9]_rA[47]_MUX_495_o ;
  wire \rA[8]_rA[47]_MUX_496_o ;
  wire \rA[7]_rA[47]_MUX_497_o ;
  wire \rA[6]_rA[47]_MUX_498_o ;
  wire \rA[5]_rA[47]_MUX_499_o ;
  wire \rA[4]_rA[47]_MUX_500_o ;
  wire \rA[3]_rA[47]_MUX_501_o ;
  wire \rA[2]_rA[47]_MUX_502_o ;
  wire \rA[1]_rA[47]_MUX_503_o ;
  wire \rA[0]_rA[47]_MUX_504_o ;
  wire \rB[47]_rB[47]_MUX_505_o ;
  wire \rB[46]_rB[47]_MUX_506_o ;
  wire \rB[45]_rB[47]_MUX_507_o ;
  wire \rB[44]_rB[47]_MUX_508_o ;
  wire \rB[43]_rB[47]_MUX_509_o ;
  wire \rB[42]_rB[47]_MUX_510_o ;
  wire \rB[41]_rB[47]_MUX_511_o ;
  wire \rB[40]_rB[47]_MUX_512_o ;
  wire \rB[39]_rB[47]_MUX_513_o ;
  wire \rB[38]_rB[47]_MUX_514_o ;
  wire \rB[37]_rB[47]_MUX_515_o ;
  wire \rB[36]_rB[47]_MUX_516_o ;
  wire \rB[35]_rB[47]_MUX_517_o ;
  wire \rB[34]_rB[47]_MUX_518_o ;
  wire \rB[33]_rB[47]_MUX_519_o ;
  wire \rB[32]_rB[47]_MUX_520_o ;
  wire \rB[31]_rB[47]_MUX_521_o ;
  wire \rB[30]_rB[47]_MUX_522_o ;
  wire \rB[29]_rB[47]_MUX_523_o ;
  wire \rB[28]_rB[47]_MUX_524_o ;
  wire \rB[27]_rB[47]_MUX_525_o ;
  wire \rB[26]_rB[47]_MUX_526_o ;
  wire \rB[25]_rB[47]_MUX_527_o ;
  wire \rB[24]_rB[47]_MUX_528_o ;
  wire \rB[23]_rB[47]_MUX_529_o ;
  wire \rB[22]_rB[47]_MUX_530_o ;
  wire \rB[21]_rB[47]_MUX_531_o ;
  wire \rB[20]_rB[47]_MUX_532_o ;
  wire \rB[19]_rB[47]_MUX_533_o ;
  wire \rB[18]_rB[47]_MUX_534_o ;
  wire \rB[17]_rB[47]_MUX_535_o ;
  wire \rB[16]_rB[47]_MUX_536_o ;
  wire \rB[15]_rB[47]_MUX_537_o ;
  wire \rB[14]_rB[47]_MUX_538_o ;
  wire \rB[13]_rB[47]_MUX_539_o ;
  wire \rB[12]_rB[47]_MUX_540_o ;
  wire \rB[11]_rB[47]_MUX_541_o ;
  wire \rB[10]_rB[47]_MUX_542_o ;
  wire \rB[9]_rB[47]_MUX_543_o ;
  wire \rB[8]_rB[47]_MUX_544_o ;
  wire \rB[7]_rB[47]_MUX_545_o ;
  wire \rB[6]_rB[47]_MUX_546_o ;
  wire \rB[5]_rB[47]_MUX_547_o ;
  wire \rB[4]_rB[47]_MUX_548_o ;
  wire \rB[3]_rB[47]_MUX_549_o ;
  wire \rB[2]_rB[47]_MUX_550_o ;
  wire \rB[1]_rB[47]_MUX_551_o ;
  wire \rB[0]_rB[47]_MUX_552_o ;
  wire \Temp[47]_Temp[45]_AND_1_o ;
  wire \Temp[47]_Temp[44]_AND_2_o ;
  wire \Temp[47]_Temp[43]_AND_3_o ;
  wire \Temp[47]_Temp[42]_AND_4_o ;
  wire \Temp[47]_Temp[41]_AND_5_o ;
  wire \Temp[47]_Temp[40]_AND_6_o ;
  wire \Temp[47]_Temp[39]_AND_7_o ;
  wire \Temp[47]_Temp[38]_AND_8_o ;
  wire \Temp[47]_Temp[37]_AND_9_o ;
  wire \Temp[47]_Temp[36]_AND_10_o ;
  wire \Temp[47]_Temp[35]_AND_11_o ;
  wire \Temp[47]_Temp[34]_AND_12_o ;
  wire \Temp[47]_Temp[33]_AND_13_o ;
  wire \Temp[47]_Temp[32]_AND_14_o ;
  wire \Temp[47]_Temp[31]_AND_15_o ;
  wire \Temp[47]_Temp[30]_AND_16_o ;
  wire \Temp[47]_Temp[29]_AND_17_o ;
  wire \Temp[47]_Temp[28]_AND_18_o ;
  wire \Temp[47]_Temp[27]_AND_19_o ;
  wire \Temp[47]_Temp[26]_AND_20_o ;
  wire \Temp[47]_Temp[25]_AND_21_o ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<7> ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<6> ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<5> ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<4> ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<3> ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<2> ;
  wire \rExp[7]_rExp[7]_mux_5_OUT<1> ;
  wire \i[3]_i[3]_wide_mux_132_OUT<3> ;
  wire \i[3]_i[3]_wide_mux_132_OUT<2> ;
  wire \i[3]_i[3]_wide_mux_132_OUT<1> ;
  wire \i[3]_i[3]_wide_mux_132_OUT<0> ;
  wire _n0845;
  wire \rA[47]_GND_1_o_add_12_OUT<47> ;
  wire \rA[47]_GND_1_o_add_12_OUT<46> ;
  wire \rA[47]_GND_1_o_add_12_OUT<45> ;
  wire \rA[47]_GND_1_o_add_12_OUT<44> ;
  wire \rA[47]_GND_1_o_add_12_OUT<43> ;
  wire \rA[47]_GND_1_o_add_12_OUT<42> ;
  wire \rA[47]_GND_1_o_add_12_OUT<41> ;
  wire \rA[47]_GND_1_o_add_12_OUT<40> ;
  wire \rA[47]_GND_1_o_add_12_OUT<39> ;
  wire \rA[47]_GND_1_o_add_12_OUT<38> ;
  wire \rA[47]_GND_1_o_add_12_OUT<37> ;
  wire \rA[47]_GND_1_o_add_12_OUT<36> ;
  wire \rA[47]_GND_1_o_add_12_OUT<35> ;
  wire \rA[47]_GND_1_o_add_12_OUT<34> ;
  wire \rA[47]_GND_1_o_add_12_OUT<33> ;
  wire \rA[47]_GND_1_o_add_12_OUT<32> ;
  wire \rA[47]_GND_1_o_add_12_OUT<31> ;
  wire \rA[47]_GND_1_o_add_12_OUT<30> ;
  wire \rA[47]_GND_1_o_add_12_OUT<29> ;
  wire \rA[47]_GND_1_o_add_12_OUT<28> ;
  wire \rA[47]_GND_1_o_add_12_OUT<27> ;
  wire \rA[47]_GND_1_o_add_12_OUT<26> ;
  wire \rA[47]_GND_1_o_add_12_OUT<25> ;
  wire \rA[47]_GND_1_o_add_12_OUT<24> ;
  wire \rA[47]_GND_1_o_add_12_OUT<23> ;
  wire \rA[47]_GND_1_o_add_12_OUT<22> ;
  wire \rA[47]_GND_1_o_add_12_OUT<21> ;
  wire \rA[47]_GND_1_o_add_12_OUT<20> ;
  wire \rA[47]_GND_1_o_add_12_OUT<19> ;
  wire \rA[47]_GND_1_o_add_12_OUT<18> ;
  wire \rA[47]_GND_1_o_add_12_OUT<17> ;
  wire \rA[47]_GND_1_o_add_12_OUT<16> ;
  wire \rA[47]_GND_1_o_add_12_OUT<15> ;
  wire \rA[47]_GND_1_o_add_12_OUT<14> ;
  wire \rA[47]_GND_1_o_add_12_OUT<13> ;
  wire \rA[47]_GND_1_o_add_12_OUT<12> ;
  wire \rA[47]_GND_1_o_add_12_OUT<11> ;
  wire \rA[47]_GND_1_o_add_12_OUT<10> ;
  wire \rA[47]_GND_1_o_add_12_OUT<9> ;
  wire \rA[47]_GND_1_o_add_12_OUT<8> ;
  wire \rA[47]_GND_1_o_add_12_OUT<7> ;
  wire \rA[47]_GND_1_o_add_12_OUT<6> ;
  wire \rA[47]_GND_1_o_add_12_OUT<5> ;
  wire \rA[47]_GND_1_o_add_12_OUT<4> ;
  wire \rA[47]_GND_1_o_add_12_OUT<3> ;
  wire \rA[47]_GND_1_o_add_12_OUT<2> ;