float_add_modue_synthesis.nlf

32位单精度浮点加法器

Release 14.2 - netgen P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -mhf -insert_glbl false -w -dir
netgen/synthesis -ofmt verilog -sim float_add_modue.ngc
float_add_modue_synthesis.v  

Reading design 'float_add_modue.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing multiple Verilog netlists for design 'float_add_modue' ...
Writing hierarchy information file
'E:\kechengsheji\ha1\netgen\synthesis\float_add_modue_synthesis_mhf_info.txt'
...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM simulation library for
   correct compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 145040 kilobytes