float_add_modue.par

32位单精度浮点加法器

Release 14.2 par P.28xd (nt64)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

SONY-VAIO::  Sat Dec 22 23:10:37 2012

par -w -intstyle ise -ol high -mt off float_add_modue_map.ncd
float_add_modue.ncd float_add_modue.pcf 


Constraints file: float_add_modue.pcf.
Loading device for application Rf_Device from file '7vx485t.nph' in environment E:\xi14.2\14.2\ISE_DS\ISE\.
   "float_add_modue" is an NCD, version 3.2, device xc7vx485t, package ffg1761, speed -2

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
   reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
   Note: For the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high".

Device speed data version:  "PRELIMINARY 1.06 2012-07-14".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                   331 out of 607,200    1%
    Number used as Flip Flops:                 331
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                      1,151 out of 303,600    1%
    Number used as logic:                    1,149 out of 303,600    1%
      Number using O6 output only:             839
      Number using O5 output only:              23
      Number using O5 and O6:                  287
      Number used as ROM:                        0
    Number used as Memory:                       0 out of 130,800    0%
    Number used exclusively as route-thrus:      2
      Number with same-slice register load:      0
      Number with same-slice carry load:         2
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   449 out of  75,900    1%
  Number of LUT Flip Flop pairs used:        1,161
    Number with an unused Flip Flop:           886 out of   1,161   76%
    Number with an unused LUT:                  10 out of   1,161    1%
    Number of fully used LUT-FF pairs:         265 out of   1,161   22%
    Number of slice register sites lost
      to control set restrictions:               0 out of 607,200    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.
  OVERMAPPING of BRAM resources should be ignored if the design is
  over-mapped for a non-BRAM resource or if placement fails.

IO Utilization:
  Number of bonded IOBs:                       374 out of     700   53%

Specific Feature Utilization:
  Number of RAMB36E1/FIFO36E1s:                  0 out of   1,030    0%
  Number of RAMB18E1/FIFO18E1s:                  0 out of   2,060    0%
  Number of BUFG/BUFGCTRLs:                      1 out of      32    3%
    Number used as BUFGs:                        1
    Number used as BUFGCTRLs:                    0
  Number of IDELAYE2/IDELAYE2_FINEDELAYs:        0 out of     700    0%
  Number of ILOGICE2/ILOGICE3/ISERDESE2s:        0 out of     700    0%
  Number of ODELAYE2/ODELAYE2_FINEDELAYs:        0 out of     700    0%
  Number of OLOGICE2/OLOGICE3/OSERDESE2s:        0 out of     700    0%
  Number of PHASER_IN/PHASER_IN_PHYs:            0 out of      56    0%
  Number of PHASER_OUT/PHASER_OUT_PHYs:          0 out of      56    0%
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHCEs:                             0 out of     168    0%
  Number of BUFRs:                               0 out of      56    0%
  Number of CAPTUREs:                            0 out of       1    0%
  Number of DNA_PORTs:                           0 out of       1    0%
  Number of DSP48E1s:                            0 out of   2,800    0%
  Number of EFUSE_USRs:                          0 out of       1    0%
  Number of FRAME_ECCs:                          0 out of       1    0%
  Number of GTXE2_CHANNELs:                      0 out of      56    0%
  Number of GTXE2_COMMONs:                       0 out of      14    0%
  Number of ICAPs:                               0 out of       2    0%
  Number of IDELAYCTRLs:                         0 out of      14    0%
  Number of IN_FIFOs:                            0 out of      56    0%
  Number of MMCME2_ADVs:                         0 out of      14    0%
  Number of OUT_FIFOs:                           0 out of      56    0%
  Number of PCIE_2_1s:                           0 out of       4    0%
  Number of PHASER_REFs:                         0 out of      14    0%
  Number of PHY_CONTROLs:                        0 out of      14    0%
  Number of PLLE2_ADVs:                          0 out of      14    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of XADCs:                               0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 1 mins 7 secs 
Finished initial Timing Analysis.  REAL time: 1 mins 7 secs 

Starting Router


Phase  1  : 6837 unrouted;      REAL time: 1 mins 45 secs 

Phase  2  : 6387 unrouted;      REAL time: 1 mins 48 secs 

Phase  3  : 2787 unrouted;      REAL time: 13 mins 1 secs 

Phase  4  : 2787 unrouted; (Par is working to improve performance)     REAL time: 13 mins 47 secs 

Updating file: float_add_modue.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Par is working to improve performance)     REAL time: 13 mins 52 secs 

Phase  6  : 0 unrouted; (Par is working to improve performance)     REAL time: 13 mins 52 secs 

Phase  7  : 0 unrouted; (Par is working to improve performance)     REAL time: 13 mins 52 secs 

Phase  8  : 0 unrouted; (Par is working to improve performance)     REAL time: 13 mins 52 secs 

Phase  9  : 0 unrouted; (Par is working to improve performance)     REAL time: 13 mins 54 secs 
Total REAL time to Router completion: 13 mins 55 secs 
Total CPU time to Router completion: 13 mins 38 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.
INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
Timing Score: 0 (Setup: 0, Hold: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net CLK | SETUP       |         N/A|     4.366ns|     N/A|           0
  _BUFGP                                    | HOLD        |     0.105ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 14 mins 45 secs 
Total CPU time to PAR completion: 14 mins 27 secs 

Peak Memory Usage:  1555 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2

Writing design to file float_add_modue.ncd



PAR done!