ha1.gise
来自「32位单精度浮点加法器」· GISE 代码 · 共 247 行 · 第 1/2 页
GISE
247 行
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356183742" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="7608659881790867392" xil_pn:start_ts="1356183742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1356183742" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="5443105512854707830" xil_pn:start_ts="1356183742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356183742" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1356183742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356183742" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1085697215601137138" xil_pn:start_ts="1356183742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356183742" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-7782322491054780976" xil_pn:start_ts="1356183742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356183742" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-3752836714191100544" xil_pn:start_ts="1356183742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356279047" xil_pn:in_ck="7229421133475730371" xil_pn:name="TRANEXT_xstsynthesize_virtex6" xil_pn:prop_ck="9123159814148876784" xil_pn:start_ts="1356279023">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="float_add_modue.lso"/>
<outfile xil_pn:name="float_add_modue.ngc"/>
<outfile xil_pn:name="float_add_modue.ngr"/>
<outfile xil_pn:name="float_add_modue.prj"/>
<outfile xil_pn:name="float_add_modue.syr"/>
<outfile xil_pn:name="float_add_modue.xst"/>
<outfile xil_pn:name="float_add_modue_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1356278320" xil_pn:in_ck="-8099079366168677821" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1626747570228242873" xil_pn:start_ts="1356278320">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1356278695" xil_pn:in_ck="3028394117158935584" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="6729356212214578081" xil_pn:start_ts="1356278673">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="float_add_modue.bld"/>
<outfile xil_pn:name="float_add_modue.ngd"/>
<outfile xil_pn:name="float_add_modue_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1356188725" xil_pn:in_ck="-2686463275842188671" xil_pn:name="TRANEXT_map_virtex7" xil_pn:prop_ck="2191181335274731413" xil_pn:start_ts="1356188396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="float_add_modue.pcf"/>
<outfile xil_pn:name="float_add_modue_map.map"/>
<outfile xil_pn:name="float_add_modue_map.mrp"/>
<outfile xil_pn:name="float_add_modue_map.ncd"/>
<outfile xil_pn:name="float_add_modue_map.ngm"/>
<outfile xil_pn:name="float_add_modue_map.xrpt"/>
<outfile xil_pn:name="float_add_modue_summary.xml"/>
<outfile xil_pn:name="float_add_modue_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1356189983" xil_pn:in_ck="-3386761911280287238" xil_pn:name="TRANEXT_par_virtex5" xil_pn:prop_ck="-4101483914851371285" xil_pn:start_ts="1356189034">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="float_add_modue.ncd"/>
<outfile xil_pn:name="float_add_modue.pad"/>
<outfile xil_pn:name="float_add_modue.par"/>
<outfile xil_pn:name="float_add_modue.ptwx"/>
<outfile xil_pn:name="float_add_modue.unroutes"/>
<outfile xil_pn:name="float_add_modue.xpi"/>
<outfile xil_pn:name="float_add_modue_pad.csv"/>
<outfile xil_pn:name="float_add_modue_pad.txt"/>
<outfile xil_pn:name="float_add_modue_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1356189983" xil_pn:in_ck="-4641794421785403267" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1356189929">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="float_add_modue.twr"/>
<outfile xil_pn:name="float_add_modue.twx"/>
</transform>
<transform xil_pn:end_ts="1356270527" xil_pn:in_ck="-2686463275842188671" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1356270525">
<status xil_pn:value="AbortedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForced"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1356190248" xil_pn:in_ck="-8099079366168685315" xil_pn:name="TRAN_postSynthesisSimModel" xil_pn:prop_ck="-9018113440635223776" xil_pn:start_ts="1356190239">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
<outfile xil_pn:name="netgen"/>
<outfile xil_pn:name="netgen/synthesis/float_add_modue_synthesis.nlf"/>
<outfile xil_pn:name="netgen/synthesis/float_add_modue_synthesis.v"/>
<outfile xil_pn:name="netgen/synthesis/float_add_modue_synthesis_mhf_info.txt"/>
</transform>
</transforms>
</generated_project>
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