_primary.vhd

来自「32位单精度浮点加法器」· VHDL 代码 · 共 21 行

library verilog;
use verilog.vl_types.all;
entity float_add_modue is
    port(
        CLK             : in     vl_logic;
        RSTn            : in     vl_logic;
        A               : in     vl_logic_vector(31 downto 0);
        B               : in     vl_logic_vector(31 downto 0);
        Result          : out    vl_logic_vector(31 downto 0);
        Start_Sig       : in     vl_logic;
        Done_Sig        : out    vl_logic_vector(3 downto 0);
        SQ_rA           : out    vl_logic_vector(56 downto 0);
        SQ_rB           : out    vl_logic_vector(56 downto 0);
        SQ_Temp         : out    vl_logic_vector(48 downto 0);
        SQ_TempA        : out    vl_logic_vector(48 downto 0);
        SQ_TempB        : out    vl_logic_vector(48 downto 0);
        SQ_rExp         : out    vl_logic_vector(9 downto 0);
        SQ_rExpDif      : out    vl_logic_vector(7 downto 0)
    );
end float_add_modue;