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📄 ha1.xise

📁 32位单精度浮点加法器
💻 XISE
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?><project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">  <header>    <!-- ISE source project file created by Project Navigator.             -->    <!--                                                                   -->    <!-- This file contains project source information including a list of -->    <!-- project source files, project and process properties.  This file, -->    <!-- along with the project source files, is sufficient to open and    -->    <!-- implement in ISE Project Navigator.                               -->    <!--                                                                   -->    <!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved. -->  </header>  <version xil_pn:ise_version="14.2" xil_pn:schema_version="2"/>  <files>    <file xil_pn:name="E:/float_add_modue/float_add_modue.v" xil_pn:type="FILE_VERILOG">      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>    </file>    <file xil_pn:name="test_test.v" xil_pn:type="FILE_VERILOG">      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>    </file>    <file xil_pn:name="float_add_modue.ucf" xil_pn:type="FILE_UCF">      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>    </file>    <file xil_pn:name="e.v" xil_pn:type="FILE_VERILOG">      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>    </file>  </files>  <properties>    <property xil_pn:name="Device" xil_pn:value="xc7vx485t" xil_pn:valueState="non-default"/>    <property xil_pn:name="Device Family" xil_pn:value="Virtex7" xil_pn:valueState="non-default"/>    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="true" xil_pn:valueState="non-default"/>    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="true" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Top" xil_pn:value="Module|float_add_modue" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Top File" xil_pn:value="E:/float_add_modue/float_add_modue.v" xil_pn:valueState="non-default"/>    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/float_add_modue" xil_pn:valueState="non-default"/>    <property xil_pn:name="Last Applied Goal" xil_pn:value="Timing Performance" xil_pn:valueState="non-default"/>    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Performance with IOB Packing;E:/xi14.2/14.2/ISE_DS/ISE/virtex7/data/virtex7_performance_with_iobpacking.xds" xil_pn:valueState="non-default"/>    <property xil_pn:name="List window" xil_pn:value="true" xil_pn:valueState="non-default"/>    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="High" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default" xil_pn:x_locked="true"/>    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>    <property xil_pn:name="Package" xil_pn:value="ffg1761" xil_pn:valueState="non-default"/>    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>    <property xil_pn:name="Place And Route Mode" xil_pn:value="Route Only" xil_pn:valueState="default" xil_pn:x_locked="true"/>    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default" xil_pn:x_locked="true"/>    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="Normal" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store non-default values only" xil_pn:valueState="non-default"/>    <property xil_pn:name="Register Balancing" xil_pn:value="Yes" xil_pn:valueState="non-default" xil_pn:x_locked="true"/>    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/float_add_modue" xil_pn:valueState="non-default"/>    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.test_test" xil_pn:valueState="non-default"/>    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="10ns" xil_pn:valueState="non-default"/>    <property xil_pn:name="Simulator" xil_pn:value="Modelsim-DE Verilog" xil_pn:valueState="non-default"/>    <property xil_pn:name="Source window" xil_pn:value="true" xil_pn:valueState="non-default"/>    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="default"/>    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>    <property xil_pn:name="Target UCF File Name" xil_pn:value="float_add_modue.ucf" xil_pn:valueState="non-default"/>    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="true" xil_pn:valueState="non-default"/>    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="E:/xi14.2/14.2/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>    <!--                                                                                  -->    <!-- The following properties are for internal use only. These should not be modified.-->    <!--                                                                                  -->    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|e" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_DesignName" xil_pn:value="ha1" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex7" xil_pn:valueState="default"/>    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-12-22T21:21:11" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="87584888EFA045BDA80349DCFC00BB90" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>  </properties>  <bindings/>  <libraries/>  <autoManagedFiles>    <!-- The following files are identified by `include statements in verilog -->    <!-- source files and are automatically managed by Project Navigator.     -->    <!--                                                                      -->    <!-- Do not hand-edit this section, as it will be overwritten when the    -->    <!-- project is analyzed based on files automatically identified as       -->    <!-- include files.                                                       -->  </autoManagedFiles></project>

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