pn_parser.xmsgs

来自「32位单精度浮点加法器」· XMSGS 代码 · 共 25 行

XMSGS
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated   -->
<!--     by the Xilinx ISE software.  Any direct editing or        -->
<!--     changes made to this file may result in unpredictable     -->
<!--     behavior or data corruption.  It is strongly advised that -->
<!--     users do not edit the contents of this file.              -->
<!--                                                               -->
<!-- Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.    -->

<messages>
<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/float_add_modue/float_add_modue.v&quot; into library work</arg>
</msg>

<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">E:/float_add_modue/float_add_modue.v</arg>&quot; Line <arg fmt="%d" index="2">1</arg>. <arg fmt="%s" index="3">Syntax error near &quot;`timescale&quot;.</arg>
</msg>

<msg type="error" file="ProjectMgmt" num="806" >&quot;<arg fmt="%s" index="1">E:/float_add_modue/float_add_modue.v</arg>&quot; Line <arg fmt="%d" index="2">62</arg>. <arg fmt="%s" index="3">Syntax error near &quot;initial&quot;.</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1845" ><arg fmt="%s" index="1">Analyzing Verilog file &quot;E:/kechengsheji/ha1/e.v&quot; into library work</arg>
</msg>

</messages>

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