ym2_42.txt

60进制减法 相比较 代码效率高 可以进行级联

library ieee;
use ieee.std_logic_1164.all;


entity ym2_42 is
	port(a:in std_logic_vector(1 downto 0);
			y:out std_logic_vector(3 downto 0));
end ym2_42;

architecture behave of ym2_42 is
	--signal ou: std_logic_vector (1 downto 0);
	--signal a: std_logic_vector (2 downto 0);
begin
	process(a)
	begin
	case a is
		when"00"=>y<="0001";
		when"01"=>y<="0010";
		when"10"=>y<="0100";
		when"11"=>y<="1000";
		when others =>y<="ZZZZ";
		--when"0000"=>y<="1111111110";
		--when"0001"=>y<="1111111101";
		--when"0010"=>y<="1111111011";
		--when"0011"=>y<="1111110111";
		--when"0100"=>y<="1111101111";
		--when"0101"=>y<="1111011111";
		--when"0110"=>y<="1110111111";
		--when"0111"=>y<="1101111111";
		--when"1000"=>y<="1011111111";
		--when"1001"=>y<="0111111111";
		--when others =>y<="1111111111";
end case;
end process;
--y0<=y(0);
--y1<=y(1);
--y2<=y(2);
--y3<=y(3);
end behave;