demultiplex.tan.rpt

是用verilog写的,解复接程序,可以把复接的反过来,一般用在解码程序中!

; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 0.771 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 0.769 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[2] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 0.768 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[3] ; clk        ; clk      ; None                        ; None                      ; 0.713 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[2] ; clk        ; clk      ; None                        ; None                      ; 0.707 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[1] ; count[1] ; clk        ; clk      ; None                        ; None                      ; 0.704 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; count[3] ; count[0] ; clk        ; clk      ; None                        ; None                      ; 0.677 ns                ;
+-------+------------------------------------------------+----------+----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+----------+-----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To  ; From Clock ;
+-------+--------------+------------+----------+-----+------------+
; N/A   ; None         ; 7.687 ns   ; count[2] ; P2e ; clk        ;
; N/A   ; None         ; 7.585 ns   ; count[3] ; P2e ; clk        ;
; N/A   ; None         ; 7.578 ns   ; count[3] ; P1e ; clk        ;
; N/A   ; None         ; 7.486 ns   ; count[0] ; P1e ; clk        ;
; N/A   ; None         ; 7.384 ns   ; count[2] ; P1e ; clk        ;
; N/A   ; None         ; 7.330 ns   ; count[2] ; Le  ; clk        ;
; N/A   ; None         ; 7.315 ns   ; count[1] ; P1e ; clk        ;
; N/A   ; None         ; 7.279 ns   ; count[0] ; P2e ; clk        ;
; N/A   ; None         ; 7.263 ns   ; count[1] ; Le  ; clk        ;
; N/A   ; None         ; 7.108 ns   ; count[1] ; P2e ; clk        ;
; N/A   ; None         ; 7.038 ns   ; count[3] ; Le  ; clk        ;
+-------+--------------+------------+----------+-----+------------+


+------------------------------------------------------------+
; tpd                                                        ;
+-------+-------------------+-----------------+--------+-----+
; Slack ; Required P2P Time ; Actual P2P Time ; From   ; To  ;
+-------+-------------------+-----------------+--------+-----+
; N/A   ; None              ; 8.708 ns        ; normal ; P2e ;
; N/A   ; None              ; 8.703 ns        ; normal ; P1e ;
; N/A   ; None              ; 8.488 ns        ; normal ; Le  ;
+-------+-------------------+-----------------+--------+-----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Aug 22 07:40:11 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off demultiplex -c demultiplex --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "count[3]" and destination register "count[1]"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.007 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y30_N4; Fanout = 7; REG Node = 'count[3]'
            Info: 2: + IC(0.468 ns) + CELL(0.539 ns) = 1.007 ns; Loc. = LC_X12_Y30_N6; Fanout = 6; REG Node = 'count[1]'
            Info: Total cell delay = 0.539 ns ( 53.53 % )
            Info: Total interconnect delay = 0.468 ns ( 46.47 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N6; Fanout = 6; REG Node = 'count[1]'
                Info: Total cell delay = 1.267 ns ( 44.41 % )
                Info: Total interconnect delay = 1.586 ns ( 55.59 % )
            Info: - Longest clock path from clock "clk" to source register is 2.853 ns
                Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N4; Fanout = 7; REG Node = 'count[3]'
                Info: Total cell delay = 1.267 ns ( 44.41 % )
                Info: Total interconnect delay = 1.586 ns ( 55.59 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clk" to destination pin "P2e" through register "count[2]" is 7.687 ns
    Info: + Longest clock path from clock "clk" to source register is 2.853 ns
        Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.586 ns) + CELL(0.542 ns) = 2.853 ns; Loc. = LC_X12_Y30_N7; Fanout = 7; REG Node = 'count[2]'
        Info: Total cell delay = 1.267 ns ( 44.41 % )
        Info: Total interconnect delay = 1.586 ns ( 55.59 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.678 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y30_N7; Fanout = 7; REG Node = 'count[2]'
        Info: 2: + IC(0.450 ns) + CELL(0.183 ns) = 0.633 ns; Loc. = LC_X12_Y30_N5; Fanout = 1; COMB Node = 'P2e~30'
        Info: 3: + IC(0.330 ns) + CELL(0.183 ns) = 1.146 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; COMB Node = 'P2e~31'
        Info: 4: + IC(1.128 ns) + CELL(2.404 ns) = 4.678 ns; Loc. = PIN_F15; Fanout = 0; PIN Node = 'P2e'
        Info: Total cell delay = 2.770 ns ( 59.21 % )
        Info: Total interconnect delay = 1.908 ns ( 40.79 % )
Info: Longest tpd from source pin "normal" to destination pin "P2e" is 8.708 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_B15; Fanout = 3; PIN Node = 'normal'
    Info: 2: + IC(3.723 ns) + CELL(0.366 ns) = 5.176 ns; Loc. = LC_X12_Y30_N3; Fanout = 1; COMB Node = 'P2e~31'
    Info: 3: + IC(1.128 ns) + CELL(2.404 ns) = 8.708 ns; Loc. = PIN_F15; Fanout = 0; PIN Node = 'P2e'
    Info: Total cell delay = 3.857 ns ( 44.29 % )
    Info: Total interconnect delay = 4.851 ns ( 55.71 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Aug 22 07:40:12 2006
    Info: Elapsed time: 00:00:02