📄 demultiplex.map.qmsg
字号:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 22 07:39:31 2006 " "Info: Processing started: Tue Aug 22 07:39:31 2006" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off demultiplex -c demultiplex " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off demultiplex -c demultiplex" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "demultiplex.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file demultiplex.v" { { "Info" "ISGN_ENTITY_NAME" "1 demultiplex " "Info: Found entity 1: demultiplex" { } { { "demultiplex.v" "" { Text "C:/Documents and Settings/new/桌面/已调试/demultiplex/demultiplex.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "demultiplex " "Info: Elaborating entity \"demultiplex\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count demultiplex.v(13) " "Warning (10235): Verilog HDL Always Construct warning at demultiplex.v(13): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "demultiplex.v" "" { Text "C:/Documents and Settings/new/桌面/已调试/demultiplex/demultiplex.v" 13 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count demultiplex.v(19) " "Warning (10235): Verilog HDL Always Construct warning at demultiplex.v(19): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "demultiplex.v" "" { Text "C:/Documents and Settings/new/桌面/已调试/demultiplex/demultiplex.v" 19 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "count demultiplex.v(25) " "Warning (10235): Verilog HDL Always Construct warning at demultiplex.v(25): variable \"count\" is read inside the Always Construct but isn't in the Always Construct's Event Control" { } { { "demultiplex.v" "" { Text "C:/Documents and Settings/new/桌面/已调试/demultiplex/demultiplex.v" 25 0 0 } } } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "15 " "Info: Implemented 15 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "3 " "Info: Implemented 3 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "9 " "Info: Implemented 9 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 22 07:39:34 2006 " "Info: Processing ended: Tue Aug 22 07:39:34 2006" { } { } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -