fpga.vhd

使用vhdl编写的一段程序。 主要功能是声音周期计算

  library ieee;
  use ieee.std_logic_1164.all;
  use work.pack.all;
  use work.components_pack.all;

  entity sppe is
    port (
      clk, rst : in  std_logic;
      adc      : in  input_type;
      en_read  : out std_logic;
      en_write : out std_logic;
      pp       : out std_logic_vector(7 downto 0)
      );
  end sppe;

  architecture structural of sppe is

    component ctrl
     port (
        clk, rst : in  std_logic;
        enable   : out en_type);
    end component;
    
    component FIR
      port (
        clk, rst, en_FIR : in  std_logic;
        x                : in  input_type;
        y                : out output_type);        
    end component;
    
    component decimate
      port (
         rst, en_decimate, clk : in  std_logic;
         dac                   : in output_type;
         sample                : out output_type);
    end component;

    component FIFO
      port (
        clk, rst, en_FIFO          : in  std_logic;
        recycle, clk_FIFO          : in  std_logic;
        x                          : in  output_type;
        y2                         : out output_type;
        y3                         : out output_type);
    end component;
    
    component clipper
      port (
        clk, en_clipper, en_peak    : in std_logic;
        y3                          : in output_type;
        peak                        : in output_type;
        data_in                     : out std_logic_vector(1 downto 0));
    end component;
     
    component comparator is
       port (
         rst, en_comparator      : in  std_logic;
         clk, en_peak            : in  std_logic;
         sample1                 : in output_type;
         sample2                 : in output_type;
         peak                    : out output_type);
    end component;

  
    component ram is
       generic(width: integer := 2;   -- used to change the memory data's width
          depth: integer := 6);   -- used to change the memery address' width during 
             -- instantiation.
       port(
           clk      : in std_logic;                           --clock
           addr     : in std_logic_vector(depth - 1 downto 0); --address bus
           cs       : in std_logic;       --chip select
           oe       : in std_logic;       --output enable
             --high for write
             --low for read
           data_in  : in std_logic_vector(width - 1 downto 0);
           data_out : out std_logic_vector(width - 1 downto 0) --read data bus
           );
    end component;
  
    component acc is
       port (
         clk, rst, en_clr : in  std_logic;
         en_acc           : in std_logic;
         data_out         : in  std_logic_vector(1 downto 0);
         result           : out std_logic_vector(7 downto 0));
    end component;
  
    component ipk_comparator is
       port (
         clk, en_ipk, en_clr     : in std_logic;
         result                  : in std_logic_vector(7 downto 0);
         pp                      : out std_logic_vector(7 downto 0));
    end component;
    
    signal enable                            : en_type;
    signal all_sample, sample, y2, y3, peak  : output_type;
    signal data_in, data_out                 : std_logic_vector(1 downto 0);
    signal result                            : std_logic_vector(7 downto 0);
    
    
  begin  -- structural
      
      en_read  <= enable.en_read;
      en_write <= enable.en_write;
    
    control : ctrl
      port map (
        clk     => clk,
        rst     => rst,
        enable  => enable);
        
    filter : fir
      port map (
        clk       => clk,
        rst       => rst,
        en_FIR    => enable.en_FIR,
        x         => adc,
        y         => all_sample);
        
    decimate_4: decimate
      port map (
        en_decimate => enable.en_decimate,
        clk         => clk,
        rst         => rst,
        dac         => all_sample,
        sample      => sample);
        
    FIFO_60:FIFO
      port map (
        clk      => clk,
        rst      => rst, 
        en_FIFO  => enable.en_FIFO, 
        clk_FIFO => enable.clk_FIFO,
        recycle  => enable.recycle,
        x        => sample,
        y2       => y2,
        y3       => y3);
        
     
    peak_comparator:comparator
      port map(
        en_comparator  => enable.en_comparator,
        en_peak        => enable.en_peak,
        rst            => rst,
        clk            => clk,
        sample1        => sample,
        sample2        => y2,
        peak           => peak);
          
    centerclipper: clipper
      port map(
        en_clipper => enable.en_clipper,
        en_peak        => enable.en_peak,
        clk        => clk,
        y3         => y3,
        peak       => peak,
        data_in    => data_in);
            
    memory: ram
      port map(
            clk      => clk,
            addr     => enable.addr,
            cs       => enable.cs,
            oe       => enable.oe,
            data_in  => data_in,
            data_out => data_out);
  
    accumulate: acc
        port map (
          clk       => clk,
          rst       => rst,
          en_clr    => enable.en_clr,
          en_acc    => enable.en_acc,
          data_out  => data_out,
          result    => result);

    ipk:ipk_comparator
      port map (
         clk      => clk,
         en_clr   => enable.en_clr,
         en_ipk   => enable.en_ipk,
         result   => result,
         pp       => pp);

  end structural;