adder8b.vhd

来自「移位相加硬件乘法器,基于FPGA的VHDL语言编写的,含有全部文件」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ADDER8B IS         
      PORT (    CIN : IN STD_LOGIC;
                  A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                  B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                  S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
              COUT : OUT STD_LOGIC  );
END ADDER8B;
ARCHITECTURE struc OF ADDER8B IS
COMPONENT ADDER4B
    PORT (   CIN :  IN STD_LOGIC;
               A :  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
               B :  IN STD_LOGIC_VECTOR(3 DOWNTO 0);
               S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
            COUT : OUT STD_LOGIC   );
END COMPONENT;
    SIGNAL CARRY_OUT : STD_LOGIC;
BEGIN
    U1 : ADDER4B                     -- 例化（安装）1个4位二进制加法器U1
    PORT MAP (  CIN => CIN,             A => A(3 DOWNTO 0),
                  B => B(3 DOWNTO 0),   S => S(3 DOWNTO 0),
               COUT => CARRY_OUT    );
    U2 : ADDER4B                     -- 例化（安装）1个4位二进制加法器U2
    PORT MAP ( CIN => CARRY_OUT, A => A(7 DOWNTO 4),
       B => B(7 DOWNTO 4), S => S(7 DOWNTO 4),COUT => COUT );
END struc;