addsub.vhd

来自「实验课的作业」· VHDL 代码 · 共 46 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addsub is

Port(
X : in std_logic_vector(3 downto 0); -- first operator
Y : in std_logic_vector(3 downto 0); -- second operator
S : in std_logic; -- select signal: 0 for add, 1 for sub
Cin : in std_logic; -- carry in
F : out std_logic_vector(3 downto 0); -- out
Cout : out std_logic
); -- carry out

end addsub;

architecture Behavioral of addsub is

component adder4 Port ( 
X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
S : out std_logic_vector(3 downto 0);
Cin : in std_logic;
Cout : out std_logic
); end component; 

SIGNAL YY : std_logic_vector(3 downto 0);

begin

	YY(0) <= S xor Y(0);
	YY(1) <= S xor Y(1);
	YY(2) <= S xor Y(2);
	YY(3) <= S xor Y(3);
	 
	U2: adder4 port map (X,YY,F,S,Cout);   

end Behavioral;