fulladder.vhd

来自「实验课的作业」· VHDL 代码 · 共 25 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladder is -- a one-bit full adder
port (
A, B, Cin: in std_logic; -- Three binary inputs
S, Cout: out std_logic); -- Two binary outputs
end fulladder;

architecture Behavioral of fulladder is

begin

S <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);

end Behavioral;