dq024_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

  DQ1_OBUF_D1_185 : X_ZERO
    port map (
      O => DQ1_OBUF_D1
    );
  DQ1_OBUF_D2_PT_0_186 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN1,
      I2 => D_0_IBUF,
      I3 => D_7_IBUF,
      I4 => NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN4,
      I5 => NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN5,
      I6 => NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN6,
      I7 => NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN7,
      O => DQ1_OBUF_D2_PT_0
    );
  DQ1_OBUF_D2_PT_1_187 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN1,
      I2 => D_0_IBUF,
      I3 => NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN3,
      I4 => NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN4,
      I5 => NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN5,
      I6 => NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN6,
      I7 => DQ1_OBUF_FBK,
      O => DQ1_OBUF_D2_PT_1
    );
  DQ1_OBUF_D2_188 : X_OR2
    port map (
      I0 => DQ1_OBUF_D2_PT_0,
      I1 => DQ1_OBUF_D2_PT_1,
      O => DQ1_OBUF_D2
    );
  DQ1_OBUF_CLKF_189 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => DQ1_OBUF_CLKF
    );
  DQ1_OBUF_RSTF_190 : X_AND2
    port map (
      I0 => REST_IBUF,
      I1 => REST_IBUF,
      O => DQ1_OBUF_RSTF
    );
  DQ20_OBUF_Q_191 : X_BUF
    port map (
      I => DQ20_OBUF_Q_12,
      O => DQ20_OBUF_Q
    );
  DQ20_OBUF_FBK_192 : X_BUF
    port map (
      I => DQ20_OBUF_Q_12,
      O => DQ20_OBUF_FBK
    );
  DQ20_OBUF_tsimcreated_xor_Q_193 : X_XOR2
    port map (
      I0 => DQ20_OBUF_D,
      I1 => DQ20_OBUF_Q_12,
      O => DQ20_OBUF_tsimcreated_xor_Q
    );
  DQ20_OBUF_tsimcreated_prld_Q_194 : X_OR2
    port map (
      I0 => DQ20_OBUF_RSTF,
      I1 => PRLD,
      O => DQ20_OBUF_tsimcreated_prld_Q
    );
  DQ20_OBUF_REG : X_FF
    port map (
      I => DQ20_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => DQ20_OBUF_CLKF,
      SET => Gnd,
      RST => DQ20_OBUF_tsimcreated_prld_Q,
      O => DQ20_OBUF_Q_12
    );
  DQ20_OBUF_D_195 : X_XOR2
    port map (
      I0 => DQ20_OBUF_D1,
      I1 => DQ20_OBUF_D2,
      O => DQ20_OBUF_D
    );
  DQ20_OBUF_D1_196 : X_ZERO
    port map (
      O => DQ20_OBUF_D1
    );
  DQ20_OBUF_D2_PT_0_197 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN1,
      I2 => NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN2,
      I3 => D_7_IBUF,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN5,
      I6 => D_4_IBUF,
      I7 => NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN7,
      O => DQ20_OBUF_D2_PT_0
    );
  DQ20_OBUF_D2_PT_1_198 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN1,
      I2 => NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN2,
      I3 => NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN3,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN5,
      I6 => D_4_IBUF,
      I7 => DQ20_OBUF_FBK,
      O => DQ20_OBUF_D2_PT_1
    );
  DQ20_OBUF_D2_199 : X_OR2
    port map (
      I0 => DQ20_OBUF_D2_PT_0,
      I1 => DQ20_OBUF_D2_PT_1,
      O => DQ20_OBUF_D2
    );
  DQ20_OBUF_CLKF_200 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => DQ20_OBUF_CLKF
    );
  DQ20_OBUF_RSTF_201 : X_AND2
    port map (
      I0 => REST_IBUF,
      I1 => REST_IBUF,
      O => DQ20_OBUF_RSTF
    );
  DQ21_OBUF_Q_202 : X_BUF
    port map (
      I => DQ21_OBUF_Q_13,
      O => DQ21_OBUF_Q
    );
  DQ21_OBUF_FBK_203 : X_BUF
    port map (
      I => DQ21_OBUF_Q_13,
      O => DQ21_OBUF_FBK
    );
  DQ21_OBUF_tsimcreated_xor_Q_204 : X_XOR2
    port map (
      I0 => DQ21_OBUF_D,
      I1 => DQ21_OBUF_Q_13,
      O => DQ21_OBUF_tsimcreated_xor_Q
    );
  DQ21_OBUF_tsimcreated_prld_Q_205 : X_OR2
    port map (
      I0 => DQ21_OBUF_RSTF,
      I1 => PRLD,
      O => DQ21_OBUF_tsimcreated_prld_Q
    );
  DQ21_OBUF_REG : X_FF
    port map (
      I => DQ21_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => DQ21_OBUF_CLKF,
      SET => Gnd,
      RST => DQ21_OBUF_tsimcreated_prld_Q,
      O => DQ21_OBUF_Q_13
    );
  DQ21_OBUF_D_206 : X_XOR2
    port map (
      I0 => DQ21_OBUF_D1,
      I1 => DQ21_OBUF_D2,
      O => DQ21_OBUF_D
    );
  DQ21_OBUF_D1_207 : X_ZERO
    port map (
      O => DQ21_OBUF_D1
    );
  DQ21_OBUF_D2_PT_0_208 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN1,
      I2 => D_0_IBUF,
      I3 => D_7_IBUF,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN5,
      I6 => D_4_IBUF,
      I7 => NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN7,
      O => DQ21_OBUF_D2_PT_0
    );
  DQ21_OBUF_D2_PT_1_209 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN1,
      I2 => D_0_IBUF,
      I3 => NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN3,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN5,
      I6 => D_4_IBUF,
      I7 => DQ21_OBUF_FBK,
      O => DQ21_OBUF_D2_PT_1
    );
  DQ21_OBUF_D2_210 : X_OR2
    port map (
      I0 => DQ21_OBUF_D2_PT_0,
      I1 => DQ21_OBUF_D2_PT_1,
      O => DQ21_OBUF_D2
    );
  DQ21_OBUF_CLKF_211 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => DQ21_OBUF_CLKF
    );
  DQ21_OBUF_RSTF_212 : X_AND2
    port map (
      I0 => REST_IBUF,
      I1 => REST_IBUF,
      O => DQ21_OBUF_RSTF
    );
  DQ22_OBUF_Q_213 : X_BUF
    port map (
      I => DQ22_OBUF_Q_14,
      O => DQ22_OBUF_Q
    );
  DQ22_OBUF_FBK_214 : X_BUF
    port map (
      I => DQ22_OBUF_Q_14,
      O => DQ22_OBUF_FBK
    );
  DQ22_OBUF_tsimcreated_xor_Q_215 : X_XOR2
    port map (
      I0 => DQ22_OBUF_D,
      I1 => DQ22_OBUF_Q_14,
      O => DQ22_OBUF_tsimcreated_xor_Q
    );
  DQ22_OBUF_tsimcreated_prld_Q_216 : X_OR2
    port map (
      I0 => DQ22_OBUF_RSTF,
      I1 => PRLD,
      O => DQ22_OBUF_tsimcreated_prld_Q
    );
  DQ22_OBUF_REG : X_FF
    port map (
      I => DQ22_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => DQ22_OBUF_CLKF,
      SET => Gnd,
      RST => DQ22_OBUF_tsimcreated_prld_Q,
      O => DQ22_OBUF_Q_14
    );
  DQ22_OBUF_D_217 : X_XOR2
    port map (
      I0 => DQ22_OBUF_D1,
      I1 => DQ22_OBUF_D2,
      O => DQ22_OBUF_D
    );
  DQ22_OBUF_D1_218 : X_ZERO
    port map (
      O => DQ22_OBUF_D1
    );
  DQ22_OBUF_D2_PT_0_219 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN0,
      I1 => D_1_IBUF,
      I2 => NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN2,
      I3 => D_7_IBUF,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN5,
      I6 => D_4_IBUF,
      I7 => NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN7,
      O => DQ22_OBUF_D2_PT_0
    );
  DQ22_OBUF_D2_PT_1_220 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN0,
      I1 => D_1_IBUF,
      I2 => NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN2,
      I3 => NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN3,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN5,
      I6 => D_4_IBUF,
      I7 => DQ22_OBUF_FBK,
      O => DQ22_OBUF_D2_PT_1
    );
  DQ22_OBUF_D2_221 : X_OR2
    port map (
      I0 => DQ22_OBUF_D2_PT_0,
      I1 => DQ22_OBUF_D2_PT_1,
      O => DQ22_OBUF_D2
    );
  DQ22_OBUF_CLKF_222 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => DQ22_OBUF_CLKF
    );
  DQ22_OBUF_RSTF_223 : X_AND2
    port map (
      I0 => REST_IBUF,
      I1 => REST_IBUF,
      O => DQ22_OBUF_RSTF
    );
  DQ23_OBUF_Q_224 : X_BUF
    port map (
      I => DQ23_OBUF_Q_15,
      O => DQ23_OBUF_Q
    );
  DQ23_OBUF_FBK_225 : X_BUF
    port map (
      I => DQ23_OBUF_Q_15,
      O => DQ23_OBUF_FBK
    );
  DQ23_OBUF_tsimcreated_xor_Q_226 : X_XOR2
    port map (
      I0 => DQ23_OBUF_D,
      I1 => DQ23_OBUF_Q_15,
      O => DQ23_OBUF_tsimcreated_xor_Q
    );
  DQ23_OBUF_tsimcreated_prld_Q_227 : X_OR2
    port map (
      I0 => DQ23_OBUF_RSTF,
      I1 => PRLD,
      O => DQ23_OBUF_tsimcreated_prld_Q
    );
  DQ23_OBUF_REG : X_FF
    port map (
      I => DQ23_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => DQ23_OBUF_CLKF,
      SET => Gnd,
      RST => DQ23_OBUF_tsimcreated_prld_Q,
      O => DQ23_OBUF_Q_15
    );
  DQ23_OBUF_D_228 : X_XOR2
    port map (
      I0 => DQ23_OBUF_D1,
      I1 => DQ23_OBUF_D2,
      O => DQ23_OBUF_D
    );
  DQ23_OBUF_D1_229 : X_ZERO
    port map (
      O => DQ23_OBUF_D1
    );
  DQ23_OBUF_D2_PT_0_230 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ23_OBUF_D2_PT_0_IN0,
      I1 => D_1_IBUF,
      I2 => D_0_IBUF,
      I3 => D_7_IBUF,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ23_OBUF_D2_PT_0_IN5,
      I6 => D_4_IBUF,
      I7 => NlwInverterSignal_DQ23_OBUF_D2_PT_0_IN7,
      O => DQ23_OBUF_D2_PT_0
    );
  DQ23_OBUF_D2_PT_1_231 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ23_OBUF_D2_PT_1_IN0,
      I1 => D_1_IBUF,
      I2 => D_0_IBUF,
      I3 => NlwInverterSignal_DQ23_OBUF_D2_PT_1_IN3,
      I4 => D_2_IBUF,
      I5 => NlwInverterSignal_DQ23_OBUF_D2_PT_1_IN5,
      I6 => D_4_IBUF,
      I7 => DQ23_OBUF_FBK,
      O => DQ23_OBUF_D2_PT_1
    );
  DQ23_OBUF_D2_232 : X_OR2
    port map (
      I0 => DQ23_OBUF_D2_PT_0,
      I1 => DQ23_OBUF_D2_PT_1,
      O => DQ23_OBUF_D2
    );
  DQ23_OBUF_CLKF_233 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => DQ23_OBUF_CLKF
    );
  DQ23_OBUF_RSTF_234 : X_AND2
    port map (
      I0 => REST_IBUF,
      I1 => REST_IBUF,
      O => DQ23_OBUF_RSTF
    );
  DQ2_OBUF_Q_235 : X_BUF
    port map (
      I => DQ2_OBUF_Q_16,
      O => DQ2_OBUF_Q
    );
  DQ2_OBUF_FBK_236 : X_BUF
    port map (
      I => DQ2_OBUF_Q_16,
      O => DQ2_OBUF_FBK
    );
  DQ2_OBUF_tsimcreated_xor_Q_237 : X_XOR2
    port map (
      I0 => DQ2_OBUF_D,
      I1 => DQ2_OBUF_Q_16,
      O => DQ2_OBUF_tsimcreated_xor_Q
    );
  DQ2_OBUF_tsimcreated_prld_Q_238 : X_OR2
    port map (
      I0 => DQ2_OBUF_RSTF,
      I1 => PRLD,
      O => DQ2_OBUF_tsimcreated_prld_Q
    );
  DQ2_OBUF_REG : X_FF
    port map (
      I => DQ2_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => DQ2_OBUF_CLKF,
      SET => Gnd,
      RST => DQ2_OBUF_tsimcreated_prld_Q,
      O => DQ2_OBUF_Q_16
    );
  DQ2_OBUF_D_239 : X_XOR2
    port map (
      I0 => DQ2_OBUF_D1,
      I1 => DQ2_OBUF_D2,
      O => DQ2_OBUF_D
    );
  DQ2_OBUF_D1_240 : X_ZERO
    port map (
      O => DQ2_OBUF_D1
    );
  DQ2_OBUF_D2_PT_0_241 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN0,
      I1 => D_1_IBUF,
      I2 => NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN2,
      I3 => D_7_IBUF,
      I4 => NlwInve