dq024_timesim.vhd

来自「xilinx xc9572 cpld 实现的伺服电机控制器」· VHDL 代码 · 共 2,142 行 · 第 1/5 页

  signal NlwInverterSignal_DQ16_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ16_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ16_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ16_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ16_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ16_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ16_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ17_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ18_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ19_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ1_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ20_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ21_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ22_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ23_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ23_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ23_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ23_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ23_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ23_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ2_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ3_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ4_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ5_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ6_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_DQ7_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ8_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_0_IN6 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_0_IN7 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_DQ9_OBUF_D2_PT_1_IN6 : STD_LOGIC; 
begin
  G_IBUF_24 : X_BUF
    port map (
      I => G,
      O => G_IBUF
    );
  D_1_IBUF_25 : X_BUF
    port map (
      I => D_1_Q,
      O => D_1_IBUF
    );
  D_0_IBUF_26 : X_BUF
    port map (
      I => D_0_Q,
      O => D_0_IBUF
    );
  WR_IBUF_27 : X_BUF
    port map (
      I => WR,
      O => WR_IBUF
    );
  REST_IBUF_28 : X_BUF
    port map (
      I => REST,
      O => REST_IBUF
    );
  D_7_IBUF_29 : X_BUF
    port map (
      I => D_7_Q,
      O => D_7_IBUF
    );
  D_2_IBUF_30 : X_BUF
    port map (
      I => D_2_Q,
      O => D_2_IBUF
    );
  D_3_IBUF_31 : X_BUF
    port map (
      I => D_3_Q,
      O => D_3_IBUF
    );
  D_4_IBUF_32 : X_BUF
    port map (
      I => D_4_Q,
      O => D_4_IBUF
    );
  DQ0_33 : X_BUF
    port map (
      I => DQ0_OBUF_Q,
      O => DQ0
    );
  DQ10_34 : X_BUF
    port map (
      I => DQ10_OBUF_Q,
      O => DQ10
    );
  DQ11_35 : X_BUF
    port map (
      I => DQ11_OBUF_Q,
      O => DQ11
    );
  DQ12_36 : X_BUF
    port map (
      I => DQ12_OBUF_Q,
      O => DQ12
    );
  DQ13_37 : X_BUF
    port map (
      I => DQ13_OBUF_Q,
      O => DQ13
    );
  DQ14_38 : X_BUF
    port map (
      I => DQ14_OBUF_Q,
      O => DQ14
    );
  DQ15_39 : X_BUF
    port map (
      I => DQ15_OBUF_Q,
      O => DQ15
    );
  DQ16_40 : X_BUF
    port map (
      I => DQ16_OBUF_Q,
      O => DQ16
    );
  DQ17_41 : X_BUF
    port map (
      I => DQ17_OBUF_Q,
      O => DQ17
    );
  DQ18_42 : X_BUF
    port map (
      I => DQ18_OBUF_Q,
      O => DQ18
    );
  DQ19_43 : X_BUF
    port map (
      I => DQ19_OBUF_Q,
      O => DQ19
    );
  DQ1_44 : X_BUF
    port map (
      I => DQ1_OBUF_Q,
      O => DQ1
    );
  DQ20_45 : X_BUF
    port map (
      I => DQ20_OBUF_Q,
      O => DQ20
    );
  DQ21_46 : X_BUF
    port map (
      I => DQ21_OBUF_Q,
      O => DQ21
    );
  DQ22_47 : X_BUF
    port map (
      I => DQ22_OBUF_Q,
      O => DQ22
    );
  DQ23_48 : X_BUF
    port map (
      I => DQ23_OBUF_Q,
      O => DQ23
    );
  DQ2_49 : X_BUF
    port map (
      I => DQ2_OBUF_Q,
      O => DQ2
    );
  DQ3_50 : X_BUF
    port map (
      I => DQ3_OBUF_Q,
      O => DQ3
    );
  DQ4_51 : X_BUF
    port map (
      I => DQ4_OBUF_Q,
      O => DQ4
    );
  DQ5_52 : X_BUF
    port map (
      I => DQ5_OBUF_Q,
      O => DQ5
    );
  DQ6_53 : X_BUF
    port map (
      I => DQ6_OBUF_Q,
      O => DQ6
    );
  DQ7_54 : X_BUF
    port map (
      I => DQ7_OBUF_Q,
      O => DQ7
    );
  DQ8_55 : X_BUF
    port map (
      I => DQ8_OBUF_Q,
      O => DQ8
    );
  DQ9_56 : X_BUF
    port map (
      I => DQ9_OBUF_Q,
      O => DQ9
    );
  DQ0_OBUF_Q_57 : X_BUF
    port map (
      I => DQ0_OBUF_Q_0,
      O => DQ0_OBUF_Q
    );
  DQ0_OBUF_FBK_58 : X_BUF
    port map (
      I => DQ0_OBUF_Q_0,
      O => DQ0_OBUF_FBK
    );
  DQ0_OBUF_tsimcreated_xor_Q_59 : X_XOR2
    port map (
      I0 => DQ0_OBUF_D,
      I1 => DQ0_OBUF_Q_0,
      O => DQ0_OBUF_tsimcreated_xor_Q
    );
  DQ0_OBUF_tsimcreated_prld_Q_60 : X_OR2
    port map (
      I0 => DQ0_OBUF_RSTF,
      I1 => PRLD,
      O => DQ0_OBUF_tsimcreated_prld_Q
    );
  DQ0_OBUF_REG : X_FF
    port map (
      I => DQ0_OBUF_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => DQ0_OBUF_CLKF,
      SET => Gnd,
      RST => DQ0_OBUF_tsimcreated_prld_Q,
      O => DQ0_OBUF_Q_0
    );
  Gnd_61 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_62 : X_ONE
    port map (
      O => Vcc
    );
  DQ0_OBUF_D_63 : X_XOR2
    port map (
      I0 => DQ0_OBUF_D1,
      I1 => DQ0_OBUF_D2,
      O => DQ0_OBUF_D
    );
  DQ0_OBUF_D1_64 : X_ZERO
    port map (
      O => DQ0_OBUF_D1
    );
  DQ0_OBUF_D2_PT_0_65 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN0,
      I1 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN1,
      I2 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN2,
      I3 => D_7_IBUF,
      I4 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN4,
      I5 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN5,
      I6 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN6,
      I7 => NlwInverterSignal_DQ0_OBUF_D2_PT_0_IN7,
      O => DQ0_OBUF_D2_PT_0
    );
  DQ0_OBUF_D2_PT_1_66 : X_AND8
    port map (
      I0 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN0,
      I1 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN1,
      I2 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN2,
      I3 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN3,
      I4 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN4,
      I5 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN5,
      I6 => NlwInverterSignal_DQ0_OBUF_D2_PT_1_IN6,
      I7 => DQ0_OBUF_FBK,
      O => DQ0_OBUF_D2_PT_1
    );
  DQ0_OBUF_D2_67 : X_OR2
    port map (
      I0 => DQ0_OBUF_D2_PT_0,
      I1 => DQ0_OBUF_D2_PT_1,
      O => DQ0_OBUF_D2
    );
  DQ0_OBUF_CLKF_68 : X_AND2
    port map (
      I0 => WR_IBUF,
      I1 => WR_IBUF,
      O => DQ0_OBUF_CLKF
    );
  DQ0_OBUF_RSTF_69 : X_AND2
    port map (
      I0 => REST_IBUF,
      I1 => REST_IBUF,
      O => DQ0_OBUF_RSTF
    );
  DQ10_OBUF_Q_70 : X_BUF
    port map (
      I => DQ10_OBUF_Q_1,
      O => DQ10_OBUF_Q
    );
  DQ10_OBUF_FBK_71 : X_BUF
    port map (
      I => DQ10_OBUF_Q_1,
      O => DQ10_OBUF_FBK