📄 alu1_routed.par
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Release 7.1.04i par H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.XCOKPATEL31:: Fri Jan 06 10:38:50 2006par -w alu1.ncd alu1_routed.ncd Constraints file: alu1.pcf.Loading device for application Rf_Device from file '2v250.nph' in environment
c:/Xilinx71. "alu1" is an NCD, version 3.1, device xc2v250, package fg456, speed -5Loading device for application Rf_Device from file '2v250.nph' in environment
c:/Xilinx71. "bm_4b_v2" is an NCD, version 3.1, device xc2v250, package fg256, speed -5The STEPPING level for this design is 1.Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)Device speed data version: "PRODUCTION 1.121 2005-07-22".Starting Guide File Processing.Loading database for application par from file: "../../Pims/add/add.ncd" "alu" is an NCD, version 3.1, device xc2v250, package fg456, speed -5Loading database for application par from file: "../../Pims/shift/shift.ncd" "alu1" is an NCD, version 3.1, device xc2v250, package fg456, speed -5Loading database for application par from file: "../../Pims/sub/sub.ncd" "alu" is an NCD, version 3.1, device xc2v250, package fg456, speed -5Finished Guide File Processing.Xilinx Place and Route Guide Results File=========================================Guide Summary Report:Design Totals: Components: Name matched: 586 out of 588 99% Total guided: 586 out of 586 100% Signals: Name matched: 554 out of 563 98% Total guided: 554 out of 554 100% Total connections guided: 1004Area Group: "AG_U1" Guide mode: "exact" Guide File: "../../Pims/add/add.ncd" Components: Name matched: 10 out of 10 100% Total guided: 10 out of 10 100% Signals: Name matched: 26 out of 28 92% Total guided: 26 out of 26 100% Total connections guided: 26Area Group: "AG_U2" Guide mode: "exact" Guide File: "../../Pims/sub/sub.ncd" Components: Name matched: 10 out of 10 100% Total guided: 10 out of 10 100% Signals: Name matched: 26 out of 27 96% Total guided: 26 out of 26 100% Total connections guided: 26Area Group: "AG_U3" Guide mode: "exact" Guide File: "../../Pims/shift/shift.ncd" Components: Name matched: 61 out of 61 100% Total guided: 61 out of 61 100% Signals: Name matched: 91 out of 91 100% Total guided: 91 out of 91 100% Total connections guided: 155Ungrouped Logic: Guide mode: "exact" Guide File: "../../Pims/add/add.ncd" Components: Name matched: 168 out of 169 99% Total guided: 168 out of 168 100% Signals: Name matched: 137 out of 139 98% Total guided: 137 out of 137 100% Total connections guided: 99 Guide File: "../../Pims/shift/shift.ncd" Components: Name matched: 169 out of 169 100% Total guided: 169 out of 169 100% Signals: Name matched: 137 out of 139 98% Total guided: 137 out of 137 100% Total connections guided: 300 Guide File: "../../Pims/sub/sub.ncd" Components: Name matched: 168 out of 169 99% Total guided: 168 out of 168 100% Signals: Name matched: 137 out of 139 98% Total guided: 137 out of 137 100% Total connections guided: 398For a detailed guide report refer to the "alu1_routed.grf" file.Device Utilization Summary: Number of BUFGMUXs 2 out of 16 12% Number of External IOBs 123 out of 200 61% Number of LOCed IOBs 123 out of 123 100% Number of SLICEs 61 out of 1536 3% Number of TBUFs 64 out of 768 8%Overall effort level (-ol): Standard (default)Placer effort level (-pl): Standard (default)Placer cost table entry (-t): 1Router effort level (-rl): Standard (default)Generating "PAR" statistics.**************************Generating Clock Report**************************WARNING:Guide:153 - The following Clock signals are not routed on the dedicated global clock routing resources. This will usually result in longer delays and higher skew for the clock load pins. This could be the result of incorrect clock placement, more than 8 clocks feeding logic in a single quadrant of the device, or incorrect logic partitioning into the quadrant(s). Check the timing report to verify the delay and skew for this netNet Name: clock_c+---------------------+--------------+------+------+------------+-------------+| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|+---------------------+--------------+------+------+------------+-------------+| U3/clockz | BUFGMUX7P| No | 14 | 0.024 | 0.776 |+---------------------+--------------+------+------+------------+-------------+| clock_c | Local| | 19 | 0.008 | 0.860 |+---------------------+--------------+------+------+------------+-------------+INFO:Par:340 - The Delay report will not be generated when running non-timing driven PAR
with effort level Standard or Medium. If a delay report is required please do
one of the following: 1) use effort level High, 2) use the following
environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
constraints for the design.Generating Pad Report.1 signals are not completely routed.WARNING:Par:100 - Design is not completely routed.Total REAL time to PAR completion: 7 secs Total CPU time to PAR completion: 7 secs Peak Memory Usage: 101 MBGuide : Placement Completed - No errors found.Guide : Routing Completed - errors found.Placer: Skipped.Router: Skipped.Number of error messages: 0Number of warning messages: 2Number of info messages: 1Writing design to file alu1_routed.ncdPAR done!
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