📄 alu.mrp
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Release 7.1.04i Map H.42Xilinx Mapping Report File for Design 'alu'Design Information------------------Command Line : map alu.ngd Target Device : xc2v250Target Package : fg456Target Speed : -5Mapper Version : virtex2 -- $Revision: 1.26.6.4 $Mapped Date : Fri Jan 06 10:37:32 2006Design Summary--------------Number of errors: 0Number of warnings: 4Logic Utilization: Number of Slice Flip Flops: 17 out of 3,072 1% Number of 4 input LUTs: 16 out of 3,072 1%Logic Distribution: Number of occupied Slices: 9 out of 1,536 1% Number of Slices containing only related logic: 9 out of 9 100% Number of Slices containing unrelated logic: 0 out of 9 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 16 out of 3,072 1% Number of bonded IOBs: 123 out of 200 61% Number of GCLKs: 1 out of 16 6% Number of hard macros: 8Total equivalent gate count for design (not including hard macros): 328Additional JTAG gate count for IOBs: 5,904Peak Memory Usage: 104 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Additional Device Resource CountsSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:LIT:243 - Logical network VCC has no load.WARNING:LIT:374 - The above warning message base_net_load_rule is repeated 4
more times for the following (max. 5 shown): GND, U1/VCC, bm16_1/VCC, bm16_2/VCC To see the details of these warning messages, please use the -detail switch.WARNING:MapLib:328 - Block U3 is not a recognized logical block. The mapper will
continue to process the design but there may be design problems if this block
does not get trimmed.WARNING:MapLib:328 - Block U2 is not a recognized logical block. The mapper will
continue to process the design but there may be design problems if this block
does not get trimmed.Section 3 - Informational-------------------------INFO:Map:110 - output buffer 'Q1_obuf[16]' driving design level port 'Q1[16]' is
being pushed into module 'U1' to enable I/O register usage. The buffer has
been renamed as 'U1/Q1_obuf[16]'.INFO:MapLib:562 - No environment variables are currently set.INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: alu symbol "alu"INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs in the
schematic.Section 4 - Removed Logic Summary--------------------------------- 3 block(s) removed 3 block(s) optimized away 3 signal(s) removedSection 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).The signal "VCC" is loadless and has been removed. Loadless block "VCC" (ONE) removed.The signal "GND" is loadless and has been removed. Loadless block "GND" (ZERO) removed.The signal "U1/VCC" is sourceless and has been removed.Unused block "U1/VCC" (ONE) removed.Optimized Block(s):TYPE BLOCKGND bm16_1/GNDGND bm16_2/GNDGND U1/GNDTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+------------------------------------------------------------------------------------------------------------------------+| A_add[0] | IOB | INPUT | LVTTL | | | | | || A_add[1] | IOB | INPUT | LVTTL | | | | | || A_add[2] | IOB | INPUT | LVTTL | | | | | || A_add[3] | IOB | INPUT | LVTTL | | | | | || A_add[4] | IOB | INPUT | LVTTL | | | | | || A_add[5] | IOB | INPUT | LVTTL | | | | | || A_add[6] | IOB | INPUT | LVTTL | | | | | || A_add[7] | IOB | INPUT | LVTTL | | | | | || A_add[8] | IOB | INPUT | LVTTL | | | | | || A_add[9] | IOB | INPUT | LVTTL | | | | | || A_add[10] | IOB | INPUT | LVTTL | | | | | || A_add[11] | IOB | INPUT | LVTTL | | | | | || A_add[12] | IOB | INPUT | LVTTL | | | | | || A_add[13] | IOB | INPUT | LVTTL | | | | | || A_add[14] | IOB | INPUT | LVTTL | | | | | || A_add[15] | IOB | INPUT | LVTTL | | | | | || A_sub[0] | IOB | INPUT | LVTTL | | | | | || A_sub[1] | IOB | INPUT | LVTTL | | | | | || A_sub[2] | IOB | INPUT | LVTTL | | | | | || A_sub[3] | IOB | INPUT | LVTTL | | | | | || A_sub[4] | IOB | INPUT | LVTTL | | | | | || A_sub[5] | IOB | INPUT | LVTTL | | | | | || A_sub[6] | IOB | INPUT | LVTTL | | | | | || A_sub[7] | IOB | INPUT | LVTTL | | | | | || A_sub[8] | IOB | INPUT | LVTTL | | | | | || A_sub[9] | IOB | INPUT | LVTTL | | | | | || A_sub[10] | IOB | INPUT | LVTTL | | | | | || A_sub[11] | IOB | INPUT | LVTTL | | | | | || A_sub[12] | IOB | INPUT | LVTTL | | | | | || A_sub[13] | IOB | INPUT | LVTTL | | | | | || A_sub[14] | IOB | INPUT | LVTTL | | | | | || A_sub[15] | IOB | INPUT | LVTTL | | | | | || B_add[0] | IOB | INPUT | LVTTL | | | | | || B_add[1] | IOB | INPUT | LVTTL | | | | | || B_add[2] | IOB | INPUT | LVTTL | | | | | || B_add[3] | IOB | INPUT | LVTTL | | | | | || B_add[4] | IOB | INPUT | LVTTL | | | | | |⌨️ 快捷键说明
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