📄 alu1.mrp
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| A_add[10] | IOB | INPUT | LVTTL | | | | | || A_add[11] | IOB | INPUT | LVTTL | | | | | || A_add[12] | IOB | INPUT | LVTTL | | | | | || A_add[13] | IOB | INPUT | LVTTL | | | | | || A_add[14] | IOB | INPUT | LVTTL | | | | | || A_add[15] | IOB | INPUT | LVTTL | | | | | || A_sub[0] | IOB | INPUT | LVTTL | | | | | || A_sub[1] | IOB | INPUT | LVTTL | | | | | || A_sub[2] | IOB | INPUT | LVTTL | | | | | || A_sub[3] | IOB | INPUT | LVTTL | | | | | || A_sub[4] | IOB | INPUT | LVTTL | | | | | || A_sub[5] | IOB | INPUT | LVTTL | | | | | || A_sub[6] | IOB | INPUT | LVTTL | | | | | || A_sub[7] | IOB | INPUT | LVTTL | | | | | || A_sub[8] | IOB | INPUT | LVTTL | | | | | || A_sub[9] | IOB | INPUT | LVTTL | | | | | || A_sub[10] | IOB | INPUT | LVTTL | | | | | || A_sub[11] | IOB | INPUT | LVTTL | | | | | || A_sub[12] | IOB | INPUT | LVTTL | | | | | || A_sub[13] | IOB | INPUT | LVTTL | | | | | || A_sub[14] | IOB | INPUT | LVTTL | | | | | || A_sub[15] | IOB | INPUT | LVTTL | | | | | || B_add[0] | IOB | INPUT | LVTTL | | | | | || B_add[1] | IOB | INPUT | LVTTL | | | | | || B_add[2] | IOB | INPUT | LVTTL | | | | | || B_add[3] | IOB | INPUT | LVTTL | | | | | || B_add[4] | IOB | INPUT | LVTTL | | | | | || B_add[5] | IOB | INPUT | LVTTL | | | | | || B_add[6] | IOB | INPUT | LVTTL | | | | | || B_add[7] | IOB | INPUT | LVTTL | | | | | || B_add[8] | IOB | INPUT | LVTTL | | | | | || B_add[9] | IOB | INPUT | LVTTL | | | | | || B_add[10] | IOB | INPUT | LVTTL | | | | | || B_add[11] | IOB | INPUT | LVTTL | | | | | || B_add[12] | IOB | INPUT | LVTTL | | | | | || B_add[13] | IOB | INPUT | LVTTL | | | | | || B_add[14] | IOB | INPUT | LVTTL | | | | | || B_add[15] | IOB | INPUT | LVTTL | | | | | || B_sub[0] | IOB | INPUT | LVTTL | | | | | || B_sub[1] | IOB | INPUT | LVTTL | | | | | || B_sub[2] | IOB | INPUT | LVTTL | | | | | || B_sub[3] | IOB | INPUT | LVTTL | | | | | || B_sub[4] | IOB | INPUT | LVTTL | | | | | || B_sub[5] | IOB | INPUT | LVTTL | | | | | || B_sub[6] | IOB | INPUT | LVTTL | | | | | || B_sub[7] | IOB | INPUT | LVTTL | | | | | || B_sub[8] | IOB | INPUT | LVTTL | | | | | || B_sub[9] | IOB | INPUT | LVTTL | | | | | || B_sub[10] | IOB | INPUT | LVTTL | | | | | || B_sub[11] | IOB | INPUT | LVTTL | | | | | || B_sub[12] | IOB | INPUT | LVTTL | | | | | || B_sub[13] | IOB | INPUT | LVTTL | | | | | || B_sub[14] | IOB | INPUT | LVTTL | | | | | || B_sub[15] | IOB | INPUT | LVTTL | | | | | || Q1[0] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[1] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[2] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[3] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[4] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[5] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[6] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[7] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[8] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[9] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[10] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[11] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[12] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[13] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[14] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[15] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q1[16] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[0] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[1] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[2] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[3] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[4] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[5] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[6] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[7] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[8] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[9] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[10] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[11] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[12] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[13] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[14] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[15] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q2[16] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[0] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[1] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[2] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[3] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[4] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[5] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[6] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[7] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[8] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[9] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[10] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[11] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[12] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[13] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[14] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[15] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || Q3[16] | IOB | OUTPUT | LVTTL | 12 | SLOW | | | || clock | IOB | INPUT | LVTTL | | | | | || reset_add | IOB | INPUT | LVTTL | | | | | || reset_shift | IOB | INPUT | LVTTL | | | | | || reset_sub | IOB | INPUT | LVTTL | | | | | || triL1 | IOB | INPUT | LVTTL | | | | | || triL2 | IOB | INPUT | LVTTL | | | | | || triR1 | IOB | INPUT | LVTTL | | | | | || triR2 | IOB | INPUT | LVTTL | | | | | |+------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group Summary------------------------------AREA_GROUP AG_U3 RANGE: SLICE_X8Y47:SLICE_X23Y0 No COMPRESSION specified for AREA_GROUP AG_U3 AREA_GROUP Logic Utilization: Number of Slice Flip Flops: 17 out of 1,536 1% Logic Distribution: Number of occupied Slices: 43 out of 768 5% Number Slices used containing only related logic: 43 out of 43 100% Total Number 4 input LUTs: 81 out of 1,536 5% Number used as logic: 81Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------This design was not run using timing mode.Section 12 - Configuration String Details--------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Additional Device Resource Counts----------------------------------------------Number of JTAG Gates for IOBs = 123Number of Equivalent Gates for Design = 655Number of RPM Macros = 0Number of Hard Macros = 8CAPTUREs = 0BSCANs = 0STARTUPs = 0PCILOGICs = 0DCMs = 0GCLKs = 2ICAPs = 018X18 Multipliers = 0Block RAMs = 0TBUFs = 0Total Registers (Flops & Latches in Slices & IOBs) not driven by LUTs = 0IOB Dual-Rate Flops not driven by LUTs = 0IOB Dual-Rate Flops = 0IOB Slave Pads = 0IOB Master Pads = 0IOB Latches not driven by LUTs = 0IOB Latches = 0IOB Flip Flops not driven by LUTs = 0IOB Flip Flops = 0Unbonded IOBs = 0Bonded IOBs = 123ORCYs = 0XORs = 0CARRY_INITs = 0CARRY_SKIPs = 0CARRY_MUXes = 0Total Shift Registers = 0Static Shift Registers = 0Dynamic Shift Registers = 016x1 ROMs = 016x1 RAMs = 032x1 RAMs = 0Dual Port RAMs = 0MUXFs = 9MULT_ANDs = 04 input LUTs used as Route-Thrus = 04 input LUTs = 81Slice Latches not driven by LUTs = 0Slice Latches = 0Slice Flip Flops not driven by LUTs = 0Slice Flip Flops = 17Slices = 43F6 Muxes = 0F5 Muxes = 9F8 Muxes = 0F7 Muxes = 0Number of LUT signals with 4 loads = 0Number of LUT signals with 3 loads = 0Number of LUT signals with 2 loads = 0Number of LUT signals with 1 load = 0NGM Average fanout of LUT = -1.#JNGM Maximum fanout of LUT = 0NGM Average fanin for LUT = -1.#IND⌨️ 快捷键说明
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