alu_routed.par

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Release 7.1.04i par H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

XCOKPATEL31::  Fri Jan 06 10:38:24 2006

par -w alu.ncd alu_routed.ncd 


Constraints file: alu.pcf.
Loading device for application Rf_Device from file '2v250.nph' in environment
c:/Xilinx71.
   "alu" is an NCD, version 3.1, device xc2v250, package fg456, speed -5
Loading device for application Rf_Device from file '2v250.nph' in environment
c:/Xilinx71.
   "bm_4b_v2" is an NCD, version 3.1, device xc2v250, package fg256, speed -5
The STEPPING level for this design is 1.

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)


Device speed data version:  "PRODUCTION 1.121 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 16      6%
   Number of External IOBs           123 out of 200    61%
      Number of LOCed IOBs           123 out of 123   100%

   Number of SLICEs                    9 out of 1536    1%
   Number of TBUFs                    64 out of 768     8%


Overall effort level (-ol):   Standard (default)
Placer effort level (-pl):    Standard (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (default)

WARNING:Par:276 - The signal reset_mult_c has no load
WARNING:Par:276 - The signal dataL[15] has no load
WARNING:Par:276 - The signal dataL[14] has no load
WARNING:Par:276 - The signal dataL[13] has no load
WARNING:Par:276 - The signal dataL[12] has no load
WARNING:Par:276 - The signal dataL[11] has no load
WARNING:Par:276 - The signal dataL[10] has no load
WARNING:Par:276 - The signal dataL[9] has no load
WARNING:Par:276 - The signal dataL[8] has no load
WARNING:Par:276 - The signal dataL[7] has no load
WARNING:Par:276 - The signal dataL[6] has no load
WARNING:Par:276 - The signal dataL[5] has no load
WARNING:Par:276 - The signal dataL[4] has no load
WARNING:Par:276 - The signal dataL[3] has no load
WARNING:Par:276 - The signal dataL[2] has no load
WARNING:Par:276 - The signal dataL[1] has no load
WARNING:Par:276 - The signal dataL[0] has no load
WARNING:Par:276 - The signal dataR[15] has no load
WARNING:Par:276 - The signal dataR[14] has no load
WARNING:Par:276 - The signal dataR[13] has no load
WARNING:Par:276 - The signal dataR[12] has no load
WARNING:Par:276 - The signal dataR[11] has no load
WARNING:Par:276 - The signal dataR[10] has no load
WARNING:Par:276 - The signal dataR[9] has no load
WARNING:Par:276 - The signal dataR[8] has no load
WARNING:Par:276 - The signal dataR[7] has no load
WARNING:Par:276 - The signal dataR[6] has no load
WARNING:Par:276 - The signal dataR[5] has no load
WARNING:Par:276 - The signal dataR[4] has no load
WARNING:Par:276 - The signal dataR[3] has no load
WARNING:Par:276 - The signal dataR[2] has no load
WARNING:Par:276 - The signal dataR[1] has no load
WARNING:Par:276 - The signal dataR[0] has no load
WARNING:Par:275 - The signal Q3_c[16] has no driver
WARNING:Par:275 - The signal Q3_c[15] has no driver
WARNING:Par:275 - The signal Q3_c[14] has no driver
WARNING:Par:275 - The signal Q3_c[13] has no driver
WARNING:Par:275 - The signal Q3_c[12] has no driver
WARNING:Par:275 - The signal Q3_c[11] has no driver
WARNING:Par:275 - The signal Q3_c[10] has no driver
WARNING:Par:275 - The signal Q3_c[9] has no driver
WARNING:Par:275 - The signal Q3_c[8] has no driver
WARNING:Par:275 - The signal Q3_c[7] has no driver
WARNING:Par:275 - The signal Q3_c[6] has no driver
WARNING:Par:275 - The signal Q3_c[5] has no driver
WARNING:Par:275 - The signal Q3_c[4] has no driver
WARNING:Par:275 - The signal Q3_c[3] has no driver
WARNING:Par:275 - The signal Q3_c[2] has no driver
WARNING:Par:275 - The signal Q3_c[1] has no driver
WARNING:Par:275 - The signal Q3_c[0] has no driver
WARNING:Par:276 - The signal reset_add_c has no load
WARNING:Par:276 - The signal A_add_c[15] has no load
WARNING:Par:276 - The signal A_add_c[14] has no load
WARNING:Par:276 - The signal A_add_c[13] has no load
WARNING:Par:276 - The signal A_add_c[12] has no load
WARNING:Par:276 - The signal A_add_c[11] has no load
WARNING:Par:276 - The signal A_add_c[10] has no load
WARNING:Par:276 - The signal A_add_c[9] has no load
WARNING:Par:276 - The signal A_add_c[8] has no load
WARNING:Par:276 - The signal A_add_c[7] has no load
WARNING:Par:276 - The signal A_add_c[6] has no load
WARNING:Par:276 - The signal A_add_c[5] has no load
WARNING:Par:276 - The signal A_add_c[4] has no load
WARNING:Par:276 - The signal A_add_c[3] has no load
WARNING:Par:276 - The signal A_add_c[2] has no load
WARNING:Par:276 - The signal A_add_c[1] has no load
WARNING:Par:276 - The signal A_add_c[0] has no load
WARNING:Par:276 - The signal B_add_c[15] has no load
WARNING:Par:276 - The signal B_add_c[14] has no load
WARNING:Par:276 - The signal B_add_c[13] has no load
WARNING:Par:276 - The signal B_add_c[12] has no load
WARNING:Par:276 - The signal B_add_c[11] has no load
WARNING:Par:276 - The signal B_add_c[10] has no load
WARNING:Par:276 - The signal B_add_c[9] has no load
WARNING:Par:276 - The signal B_add_c[8] has no load
WARNING:Par:276 - The signal B_add_c[7] has no load
WARNING:Par:276 - The signal B_add_c[6] has no load
WARNING:Par:276 - The signal B_add_c[5] has no load
WARNING:Par:276 - The signal B_add_c[4] has no load
WARNING:Par:276 - The signal B_add_c[3] has no load
WARNING:Par:276 - The signal B_add_c[2] has no load
WARNING:Par:276 - The signal B_add_c[1] has no load
WARNING:Par:276 - The signal B_add_c[0] has no load
WARNING:Par:275 - The signal Q1_c[16] has no driver
WARNING:Par:275 - The signal Q1_c[15] has no driver
WARNING:Par:275 - The signal Q1_c[14] has no driver
WARNING:Par:275 - The signal Q1_c[13] has no driver
WARNING:Par:275 - The signal Q1_c[12] has no driver
WARNING:Par:275 - The signal Q1_c[11] has no driver
WARNING:Par:275 - The signal Q1_c[10] has no driver
WARNING:Par:275 - The signal Q1_c[9] has no driver
WARNING:Par:275 - The signal Q1_c[8] has no driver
WARNING:Par:275 - The signal Q1_c[7] has no driver
WARNING:Par:275 - The signal Q1_c[6] has no driver
WARNING:Par:275 - The signal Q1_c[5] has no driver
WARNING:Par:275 - The signal Q1_c[4] has no driver
WARNING:Par:275 - The signal Q1_c[3] has no driver
WARNING:Par:275 - The signal Q1_c[2] has no driver
WARNING:Par:275 - The signal Q1_c[1] has no driver
WARNING:Par:275 - The signal Q1_c[0] has no driver

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989fac) REAL time: 1 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 1 secs 

Phase 3.2
WARNING:Place:490 - A clock IOB / clock component pair have been found that are
   not placed at an optimal clock IOB / clock site pair.  The clock component
   <clock_ibuf/BUFG> is placed at site BUFGMUX4S.  The clock IO site that is
   paired with this clock buffer using I0 inputsite is PAD24.  The IO component
   clock is placed at site PAD21.  This will not allow the use of the fast path
   between the IO and the Clock buffer.  You may want to analyze why this
   problem exists and correct it.  This is not an error so processing will
   continue.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 1 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 1 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 1 secs 

Phase 7.8
.
Phase 7.8 (Checksum:9b21d3) REAL time: 1 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 1 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 1 secs 

Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 1 secs 

Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 1 secs 

Writing design to file alu_routed.ncd


Total REAL time to Placer completion: 1 secs 
Total CPU time to Placer completion: 1 secs 

Starting Router

Phase 1: 266 unrouted;       REAL time: 2 secs 

Phase 2: 257 unrouted;       REAL time: 2 secs 

Phase 3: 140 unrouted;       REAL time: 2 secs 


IMPORTANT MSG: UNROUTABLE DESIGN; CHANGE PLACEMENT or EASE CONSTRAINTS
Phase 4: 131 unrouted;       REAL time: 2 secs 


Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 2 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|             clock_c |     BUFGMUX4S|Yes   |    9 |  0.008     |  0.794      |
+---------------------+--------------+------+------+------------+-------------+

INFO:Par:340 - 
   The Delay report will not be generated when running non-timing driven PAR
   with effort level Standard or Medium. If a delay report is required please do
   one of the following:  1) use effort level High, 2) use the following
   environment variable "XIL_PAR_GENERATE_DLY_REPORT", 3) create Timing
   constraints for the design.
Generating Pad Report.

5 signals are not completely routed.

WARNING:Par:100 - Design is not completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  104 MB

Placement: Completed - No errors found.
Routing: Completed - errors found.

Number of error messages: 0
Number of warning messages: 102
Number of info messages: 1

Writing design to file alu_routed.ncd



PAR done!