ss7160.tim

该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻辑代码,其中包括了VHDL及原理图.

                           Performance Summary Report
                           --------------------------

Design:     ss7160
Device:     XC95144-15-PQ160 
Program:    Timing Report Generator:  version C.22
Date:       Mon Jul 16 19:44:31 2001

Performance Summary: 

Pad to Pad (tPD)                          :         47.0ns (3 macrocell levels)
Pad 'N_CHOLD' to Pad 'SD0'                                        

Clock net 'SAEN' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SAEN' to Output Pad 'SD0'                              (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SAEN'                                                  (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'N_SIOW' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'N_SIOW' to Output Pad 'SD0'                            (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'N_SIOW'                                                (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA8' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA8' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA8'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA9' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA9' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA9'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA3' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA3' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA3'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA4' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA4' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA4'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA5' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA5' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA5'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA6' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA6' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA6'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'SA7' path delays:

Clock Pad to Output Pad (tCO)             :         78.0ns (5 macrocell levels)
Clock Pad 'SA7' to Output Pad 'SD0'                               (Pterm Clock)

Setup to Clock at the Pad (tSU)           :         -5.5ns (0 macrocell levels)
Data signal 'SD0' to DFF D input Pin at 'U1/CSE_Q<0>.D'
Clock pad 'SA7'                                                   (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'N_DC4' path delays:

Clock Pad to Output Pad (tCO)             :         29.0ns (2 macrocell levels)
Clock Pad 'N_DC4' to Output Pad 'N_TSD'                           (Pterm Clock)

Clock to Setup (tCYC)                     :         10.5ns (1 macrocell levels)
Clock to Q, net '\$I37/iDCounter<0>.Q' to DFF Setup(D) at '\$I37/iDCounter<0>.D'(Pterm Clock)
Target FF drives output net '\$I37/iDCounter<0>'

Setup to Clock at the Pad (tSU)           :          4.0ns (0 macrocell levels)
Data signal 'N_DF0' to DFF D input Pin at '\$I37/iDCounter<0>.D'
Clock pad 'N_DC4'                                                 (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

Clock net 'N_CC4' path delays:

Clock Pad to Output Pad (tCO)             :         29.0ns (2 macrocell levels)
Clock Pad 'N_CC4' to Output Pad 'N_TSC'                           (Pterm Clock)

Clock to Setup (tCYC)                     :         18.0ns (1 macrocell levels)
Clock to Q, net '\$I37/iCCounter<0>.Q' to DFF Setup(D) at '\$I37/iCCounter<1>.D'(Pterm Clock)
Target FF drives output net '\$I37/iCCounter<1>'

Setup to Clock at the Pad (tSU)           :          4.0ns (0 macrocell levels)
Data signal 'N_CF0' to DFF D input Pin at '\$I37/iCCounter<0>.D'
Clock pad 'N_CC4'                                                 (Pterm Clock)

                          Minimum Clock Period: 18.0ns
                     Maximum Internal Clock Speed: 55.5Mhz
                            (Limited by Cycle Time)

Clock net 'N_BC4' path delays:

Clock Pad to Output Pad (tCO)             :         29.0ns (2 macrocell levels)
Clock Pad 'N_BC4' to Output Pad 'N_TSB'                           (Pterm Clock)

Clock to Setup (tCYC)                     :         18.0ns (1 macrocell levels)
Clock to Q, net '\$I37/iBCounter<0>.Q' to TFF Setup(D) at '\$I37/iBCounter<5>.D'(Pterm Clock)
Target FF drives output net '\$I37/iBCounter<5>'

Setup to Clock at the Pad (tSU)           :          4.0ns (0 macrocell levels)
Data signal 'N_BF0' to DFF D input Pin at '\$I37/iBCounter<0>.D'
Clock pad 'N_BC4'                                                 (Pterm Clock)

                          Minimum Clock Period: 18.0ns
                     Maximum Internal Clock Speed: 55.5Mhz
                            (Limited by Cycle Time)

Clock net 'N_AC4' path delays:

Clock Pad to Output Pad (tCO)             :         29.0ns (2 macrocell levels)
Clock Pad 'N_AC4' to Output Pad 'N_TSA'                           (Pterm Clock)

Clock to Setup (tCYC)                     :         10.5ns (1 macrocell levels)
Clock to Q, net '\$I37/iACounter<0>.Q' to DFF Setup(D) at '\$I37/iACounter<0>.D'(Pterm Clock)
Target FF drives output net '\$I37/iACounter<0>'

Setup to Clock at the Pad (tSU)           :          4.0ns (0 macrocell levels)
Data signal 'N_AF0' to DFF D input Pin at '\$I37/iACounter<0>.D'
Clock pad 'N_AC4'                                                 (Pterm Clock)

                          Minimum Clock Period: 14.0ns
                     Maximum Internal Clock Speed: 71.4Mhz
                         (Limited by Clock Pulse Width)

--------------------------------------------------------------------------------
                            Pad to Pad (tPD) (nsec)

\ From      A     B     C     C     C     C     C     D     N     N     N     N
 \          R     R     P     P     P     P     R     R     _     _     _     _
  \         E     E     U     U     U     U     E     E     A     A     A     A
   \        A     A     A     A     R     W     A     A     D     H     H     I
    \       D     D     1     1     D     R     D     D     A     L     O     N
     \                  3     4                             S     D     L     T
      \                                                           A     D