ss7160.tim
来自「该代码为配合7号信令模块MK50H27的cpld(xilinx 95144)的逻」· TIM 代码 · 共 831 行 · 第 1/4 页
TIM
831 行
\ C C C C I
\ 4 4 4 4 O
\ W
\
To \------------------------------------------------------------------------
AREAD 67.0 67.0 67.0 67.0 67.0 67.0 67.0 67.0
BREAD 67.0 67.0 67.0 67.0 67.0 67.0 67.0 67.0
CREAD 59.5 59.5 59.5 59.5 59.5 59.5 59.5 59.5
DREAD 72.5 72.5 72.5 72.5 72.5 72.5 72.5 72.5
LED0 29.0 29.0 29.0 29.0 29.0 29.0 29.0
LED1 29.0 29.0 29.0 29.0 29.0 29.0 29.0
LED2 29.0 29.0 29.0 29.0 29.0 29.0 29.0
LED3 29.0 29.0 29.0 29.0 29.0 29.0 29.0
N_ACS 55.5 55.5 55.5 55.5 55.5 55.5 55.5 55.5
N_ADAS 59.5 59.5 59.5 59.5 59.5 59.5 59.5 59.5
N_AHLDA 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_ARST 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_ASCE 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_BCS 55.5 55.5 55.5 55.5 55.5 55.5 55.5 55.5
N_BDAS 59.5 59.5 59.5 59.5 59.5 59.5 59.5 59.5
N_BHLDA 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_BRST 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_BSCE 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_CCS 55.5 55.5 55.5 55.5 55.5 55.5 55.5 55.5
N_CDAS 67.0 67.0 67.0 67.0 67.0 67.0 67.0 67.0
N_CHLDA 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_CRST 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_CSCE 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_DCS 55.5 55.5 55.5 55.5 55.5 55.5 55.5 55.5
N_DDAS 72.5 72.5 72.5 72.5 72.5 72.5 72.5 72.5
N_DHLDA 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_DRST 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_DSCE 46.0 46.0 46.0 46.0 46.0 46.0 46.0 46.0
N_TSA 29.0
N_TSB 29.0
N_TSC 29.0
N_TSD 29.0
RUN 29.0 29.0 29.0 29.0 29.0 29.0 29.0
SD0 78.0 78.0 78.0 78.0 78.0 78.0 78.0 78.0
--------------------------------------------------------------------------------
Clock Pad to Output Pad (tCO) (nsec)
\ From S
\ A
\ E
\ N
\
\
\
To \------
AREAD 67.0
BREAD 67.0
CREAD 59.5
DREAD 72.5
LED0 29.0
LED1 29.0
LED2 29.0
LED3 29.0
N_ACS 55.5
N_ADAS 59.5
N_AHLDA 46.0
N_ARST 46.0
N_ASCE 46.0
N_BCS 55.5
N_BDAS 59.5
N_BHLDA 46.0
N_BRST 46.0
N_BSCE 46.0
N_CCS 55.5
N_CDAS 67.0
N_CHLDA 46.0
N_CRST 46.0
N_CSCE 46.0
N_DCS 55.5
N_DDAS 72.5
N_DHLDA 46.0
N_DRST 46.0
N_DSCE 46.0
N_TSA
N_TSB
N_TSC
N_TSD
RUN 29.0
SD0 78.0
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU) (nsec)
\ From N N N N N S S
\ _ _ _ _ _ A A
\ A B C D S 3 4
\ C C C C I
\ 4 4 4 4 O
\ W
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
\
To \------------------------------------------
N_AF0 4.0
N_BF0 4.0
N_CF0 4.0
N_DF0 4.0
SD0 -5.5 -5.5 -5.5
SD1 -13.0 -13.0 -13.0
SD2 -13.0 -13.0 -13.0
SD3 -13.0 -13.0
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU) (nsec)
\ From S S S S S S U
\ A A A A A A 1
\ 5 6 7 8 9 E /
\ N C
\ S
\ E
\ _
\ Q
\ <
\ 2
\ >
\ /
\ U
\ 1
\ /
\ C
\ S
\ E
\ _
\ Q
\ <
\ 2
\ >
\ _
\ C
\ L
\ K
\ F
\ _
\ _
\ $
\ I
\ N
\ T
\ .
\ D
\ 1
To \------------------------------------------
N_AF0
N_BF0
N_CF0
N_DF0
SD0 -5.5 -5.5 -5.5 -5.5 -5.5 -5.5 2.0
SD1 -13.0 -13.0 -13.0 -13.0 -13.0 -13.0 -5.5
SD2 -13.0 -13.0 -13.0 -13.0 -13.0 -13.0 -5.5
SD3 -13.0 -13.0 -13.0 -13.0 -13.0 -13.0
--------------------------------------------------------------------------------
Setup to Clock at Pad (tSU) (nsec)
\ From U \ \
\ 1 $ $
\ / N N
\ Q e e
\ < t t
\ 3 0 0
\ > 0 0
\ / 0 0
\ U 4 4
\ 1 0 1
\ / _ _
\ Q / /
\ < \ \
\ 3 $ $
\ > N N
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