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本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

Started process "Place & Route".





Constraints file: compact_divider.pcf

Loading device database for application Par from file "compact_divider_map.ncd".
   "compact_divider" is an NCD, version 2.38, device xc2s200, package pq208,
speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            17 out of 140    12%
      Number of LOCed External IOBs    0 out of 17      0%

   Number of SLICEs                   28 out of 2352    1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896f1) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:99b181) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file compact_divider.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 183 unrouted;       REAL time: 0 secs 

Phase 2: 183 unrouted;       REAL time: 0 secs 

Phase 3: 36 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file compact_divider.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Jul 13 10:54:48 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module compact_divider . . .
PAR command line: par -w -intstyle ise -ol std -t 1 compact_divider_map.ncd compact_divider.ncd compact_divider.pcf
PAR completed successfully



Started process "Generate Post-Place & Route Simulation Model".

Completed process "Generate Post-Place & Route Simulation Model".


WARNING:HDLParsers:3215 - Unit work/COMPACT_DIVIDER is now defined in a
   different file: was d:/fpga/仿真/divider/compact_divider.vhdl, now is
   D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl
WARNING:HDLParsers:3215 - Unit work/COMPACT_DIVIDER/BEHAVIORAL is now defined in
   a different file: was d:/fpga/仿真/divider/compact_divider.vhdl, now is
   D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl
Compiling vhdl file D:/FPGA/仿真/Divider_定点除法器/compact_divider.vhdl in
Library work.
Entity <compact_divider> (Architecture <behavioral>) compiled.



Project Navigator Auto-Make Log File
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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\fpga\仿真\divider_定点除法器/_ngo -i
-p xc2s200-pq208-5 devider.ngc devider.ngd 

Reading NGO file "D:/FPGA/仿真/Divider_定点除法器/devider.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 39140 kilobytes

Writing NGD file "devider.ngd" ...

Writing NGDBUILD log file "devider.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s200pq208-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of 4 input LUTs:            50 out of  4,704    1%
Logic Distribution:
    Number of occupied Slices:                          28 out of  2,352    1%
    Number of Slices containing only related logic:     28 out of     28  100%
    Number of Slices containing unrelated logic:         0 out of     28    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:           56 out of  4,704    1%
      Number used as logic:                        50
      Number used as a route-thru:                  6
   Number of bonded IOBs:            17 out of    140   12%

Total equivalent gate count for design:  420
Additional JTAG gate count for IOBs:  816
Peak Memory Usage:  63 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "devider_map.mrp" for details.
Completed process "Map".

Mapping Module devider . . .
MAP command line:
map -intstyle ise -p xc2s200-pq208-5 -cm area -pr b -k 4 -c 100 -tx off -o devider_map.ncd devider.ngd devider.pcf
Mapping Module devider: DONE



Started process "Place & Route".





Constraints file: devider.pcf

Loading device database for application Par from file "devider_map.ncd".
   "devider" is an NCD, version 2.38, device xc2s200, package pq208, speed -5
Loading device for application Par from file 'v200.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            17 out of 140    12%
      Number of LOCed External IOBs    0 out of 17      0%

   Number of SLICEs                   28 out of 2352    1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896f1) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:99b181) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file devider.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 183 unrouted;       REAL time: 2 secs 

Phase 2: 183 unrouted;       REAL time: 2 secs 

Phase 3: 36 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  53 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file devider.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Jul 13 10:57:56 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module devider . . .
PAR command line: par -w -intstyle ise -ol std -t 1 devider_map.ncd devider.ncd devider.pcf
PAR completed successfully



Project Navigator Auto-Make Log File
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Started process "Generate Post-Place & Route Simulation Model".

Completed process "Generate Post-Place & Route Simulation Model".


WARNING:HDLParsers:3215 - Unit work/DEVIDER is now defined in a different file:
   was d:/fpga/仿真/divider/devider.vhdl, now is
   D:/FPGA/仿真/Divider_定点除法器/devider.vhdl
WARNING:HDLParsers:3215 - Unit work/DEVIDER/BEHAVIORAL is now defined in a
   different file: was d:/fpga/仿真/divider/devider.vhdl, now is
   D:/FPGA/仿真/Divider_定点除法器/devider.vhdl
Compiling vhdl file D:/FPGA/仿真/Divider_定点除法器/devider.vhdl in Library
work.
Entity <devider> (Architecture <behavioral>) compiled.



Project Navigator Auto-Make Log File
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