devider_timesim.vhd

本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.

-- Xilinx Vhdl netlist produced by netgen application (version G.29)
-- Command       : -intstyle ise -s 5 -pcf devider.pcf -ngm devider.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim devider.ncd devider_timesim.vhd 
-- Input file    : devider.ncd
-- Output file   : devider_timesim.vhd
-- Design name   : devider
-- # of Entities : 1
-- Xilinx        : C:/Xilinx
-- Device        : 2s200pq208-5 (PRODUCTION 1.27 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity devider is
  port (
    err : out STD_LOGIC; 
    rest : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    y : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    b : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    a : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end devider;

architecture Structure of devider is
  signal err_OBUF : STD_LOGIC; 
  signal y_0_OBUF : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_17 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_12 : STD_LOGIC; 
  signal rest_0_OBUF : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_6 : STD_LOGIC; 
  signal rest_1_OBUF : STD_LOGIC; 
  signal rest_2_OBUF : STD_LOGIC; 
  signal a_0_IBUF : STD_LOGIC; 
  signal rest_3_OBUF : STD_LOGIC; 
  signal a_1_IBUF : STD_LOGIC; 
  signal a_2_IBUF : STD_LOGIC; 
  signal a_3_IBUF : STD_LOGIC; 
  signal b_0_IBUF : STD_LOGIC; 
  signal b_1_IBUF : STD_LOGIC; 
  signal b_2_IBUF : STD_LOGIC; 
  signal b_3_IBUF : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_4 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_15 : STD_LOGIC; 
  signal Msub_n0012_inst_cy_19 : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_19 : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_20 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_10 : STD_LOGIC; 
  signal Msub_n0009_inst_cy_19 : STD_LOGIC; 
  signal Msub_n0009_inst_lut2_18 : STD_LOGIC; 
  signal Msub_n0009_inst_lut2_19 : STD_LOGIC; 
  signal Msub_n0009_inst_lut2_20 : STD_LOGIC; 
  signal Msub_n0010_inst_cy_19 : STD_LOGIC; 
  signal Msub_n0011_inst_cy_19 : STD_LOGIC; 
  signal Msub_n0011_inst_lut2_20 : STD_LOGIC; 
  signal CHOICE13 : STD_LOGIC; 
  signal CHOICE21 : STD_LOGIC; 
  signal CHOICE9 : STD_LOGIC; 
  signal CHOICE11 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal err_ENABLE : STD_LOGIC; 
  signal err_TORGTS : STD_LOGIC; 
  signal err_OUTMUX : STD_LOGIC; 
  signal y_0_ENABLE : STD_LOGIC; 
  signal y_0_TORGTS : STD_LOGIC; 
  signal y_0_OUTMUX : STD_LOGIC; 
  signal y_1_ENABLE : STD_LOGIC; 
  signal y_1_TORGTS : STD_LOGIC; 
  signal y_1_OUTMUX : STD_LOGIC; 
  signal y_1_ODNOT : STD_LOGIC; 
  signal y_2_ENABLE : STD_LOGIC; 
  signal y_2_TORGTS : STD_LOGIC; 
  signal y_2_OUTMUX : STD_LOGIC; 
  signal y_2_ODNOT : STD_LOGIC; 
  signal rest_0_ENABLE : STD_LOGIC; 
  signal rest_0_TORGTS : STD_LOGIC; 
  signal rest_0_OUTMUX : STD_LOGIC; 
  signal y_3_ENABLE : STD_LOGIC; 
  signal y_3_TORGTS : STD_LOGIC; 
  signal y_3_OUTMUX : STD_LOGIC; 
  signal y_3_ODNOT : STD_LOGIC; 
  signal rest_1_ENABLE : STD_LOGIC; 
  signal rest_1_TORGTS : STD_LOGIC; 
  signal rest_1_OUTMUX : STD_LOGIC; 
  signal rest_2_ENABLE : STD_LOGIC; 
  signal rest_2_TORGTS : STD_LOGIC; 
  signal rest_2_OUTMUX : STD_LOGIC; 
  signal a_0_IBUF_0 : STD_LOGIC; 
  signal rest_3_ENABLE : STD_LOGIC; 
  signal rest_3_TORGTS : STD_LOGIC; 
  signal rest_3_OUTMUX : STD_LOGIC; 
  signal a_1_IBUF_1 : STD_LOGIC; 
  signal a_2_IBUF_2 : STD_LOGIC; 
  signal a_3_IBUF_3 : STD_LOGIC; 
  signal b_0_IBUF_4 : STD_LOGIC; 
  signal b_1_IBUF_5 : STD_LOGIC; 
  signal b_2_IBUF_6 : STD_LOGIC; 
  signal b_3_IBUF_7 : STD_LOGIC; 
  signal Mcompar_n0005_inst_lut2_3 : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_4_CYMUXG : STD_LOGIC; 
  signal Mcompar_n0005_inst_lut2_4 : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_3 : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_4_LOGIC_ZERO : STD_LOGIC; 
  signal Mcompar_n0005_inst_lut2_5 : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_6_CYMUXG : STD_LOGIC; 
  signal Mcompar_n0005_inst_lut2_6 : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_5 : STD_LOGIC; 
  signal Mcompar_n0005_inst_cy_6_CYINIT : STD_LOGIC; 
  signal Mcompar_n0007_inst_lut2_14 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_15_CYMUXG : STD_LOGIC; 
  signal Mcompar_n0007_inst_lut2_15 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_14 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_15_LOGIC_ZERO : STD_LOGIC; 
  signal Mcompar_n0007_inst_lut2_16 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_17_CYMUXG : STD_LOGIC; 
  signal Mcompar_n0007_inst_lut2_17 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_16 : STD_LOGIC; 
  signal Mcompar_n0007_inst_cy_17_CYINIT : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_18 : STD_LOGIC; 
  signal Q_n0016_4_XORF : STD_LOGIC; 
  signal Q_n0016_4_CYMUXG : STD_LOGIC; 
  signal Q_n0016_4_XORG : STD_LOGIC; 
  signal Q_n0016_4_GROM : STD_LOGIC; 
  signal Msub_n0012_inst_cy_18 : STD_LOGIC; 
  signal Q_n0016_4_CYINIT : STD_LOGIC; 
  signal Q_n0016_4_LOGIC_ONE : STD_LOGIC; 
  signal Q_n0016_6_FROM : STD_LOGIC; 
  signal Q_n0016_6_XORF : STD_LOGIC; 
  signal Q_n0016_6_XORG : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_21 : STD_LOGIC; 
  signal Msub_n0012_inst_cy_20 : STD_LOGIC; 
  signal Q_n0016_6_CYINIT : STD_LOGIC; 
  signal Mcompar_n0006_inst_lut2_9 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_10_CYMUXG : STD_LOGIC; 
  signal Mcompar_n0006_inst_lut2_10 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_9 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_10_LOGIC_ZERO : STD_LOGIC; 
  signal Mcompar_n0006_inst_lut2_11 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_12_CYMUXG : STD_LOGIC; 
  signal Mcompar_n0006_inst_lut2_12 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_11 : STD_LOGIC; 
  signal Mcompar_n0006_inst_cy_12_CYINIT : STD_LOGIC; 
  signal Q_n0013_4_FROM : STD_LOGIC; 
  signal Q_n0013_4_XORF : STD_LOGIC; 
  signal Q_n0013_4_CYMUXG : STD_LOGIC; 
  signal Q_n0013_4_XORG : STD_LOGIC; 
  signal Q_n0013_4_GROM : STD_LOGIC; 
  signal Msub_n0009_inst_cy_18 : STD_LOGIC; 
  signal Q_n0013_4_CYINIT : STD_LOGIC; 
  signal Q_n0013_4_LOGIC_ONE : STD_LOGIC; 
  signal Q_n0013_6_FROM : STD_LOGIC; 
  signal Q_n0013_6_XORF : STD_LOGIC; 
  signal Q_n0013_6_XORG : STD_LOGIC; 
  signal Msub_n0009_inst_lut2_21 : STD_LOGIC; 
  signal Msub_n0009_inst_cy_20 : STD_LOGIC; 
  signal Q_n0013_6_CYINIT : STD_LOGIC; 
  signal Msub_n0010_inst_lut2_18 : STD_LOGIC; 
  signal Q_n0014_4_XORF : STD_LOGIC; 
  signal Q_n0014_4_CYMUXG : STD_LOGIC; 
  signal Q_n0014_4_XORG : STD_LOGIC; 
  signal Msub_n0010_inst_lut2_19 : STD_LOGIC; 
  signal Msub_n0010_inst_cy_18 : STD_LOGIC; 
  signal Q_n0014_4_CYINIT : STD_LOGIC; 
  signal Q_n0014_4_LOGIC_ONE : STD_LOGIC; 
  signal Msub_n0010_inst_lut2_20 : STD_LOGIC; 
  signal Q_n0014_6_XORF : STD_LOGIC; 
  signal Q_n0014_6_XORG : STD_LOGIC; 
  signal Msub_n0010_inst_lut2_21 : STD_LOGIC; 
  signal Msub_n0010_inst_cy_20 : STD_LOGIC; 
  signal Q_n0014_6_CYINIT : STD_LOGIC; 
  signal Msub_n0011_inst_lut2_18 : STD_LOGIC; 
  signal Q_n0015_4_XORF : STD_LOGIC; 
  signal Q_n0015_4_CYMUXG : STD_LOGIC; 
  signal Q_n0015_4_XORG : STD_LOGIC; 
  signal Msub_n0011_inst_lut2_19 : STD_LOGIC; 
  signal Msub_n0011_inst_cy_18 : STD_LOGIC; 
  signal Q_n0015_4_CYINIT : STD_LOGIC; 
  signal Q_n0015_4_LOGIC_ONE : STD_LOGIC; 
  signal Q_n0015_6_FROM : STD_LOGIC; 
  signal Q_n0015_6_XORF : STD_LOGIC; 
  signal Q_n0015_6_XORG : STD_LOGIC; 
  signal Msub_n0011_inst_lut2_21 : STD_LOGIC; 
  signal Msub_n0011_inst_cy_20 : STD_LOGIC; 
  signal Q_n0015_6_CYINIT : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_20_FROM : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_20_GROM : STD_LOGIC; 
  signal Q_n0013_0_FROM : STD_LOGIC; 
  signal Q_n0013_0_GROM : STD_LOGIC; 
  signal Q_n0013_1_FROM : STD_LOGIC; 
  signal Q_n0013_1_GROM : STD_LOGIC; 
  signal Q_n0013_2_FROM : STD_LOGIC; 
  signal Q_n0013_2_GROM : STD_LOGIC; 
  signal Q_n0013_3_FROM : STD_LOGIC; 
  signal Q_n0013_3_GROM : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_19_FROM : STD_LOGIC; 
  signal Msub_n0012_inst_lut2_19_GROM : STD_LOGIC; 
  signal Q_n0019_0_FROM : STD_LOGIC; 
  signal Q_n0019_0_GROM : STD_LOGIC; 
  signal Q_n0019_1_FROM : STD_LOGIC; 
  signal Q_n0019_1_GROM : STD_LOGIC; 
  signal CHOICE9_FROM : STD_LOGIC; 
  signal CHOICE9_GROM : STD_LOGIC; 
  signal err_OBUF_FROM : STD_LOGIC; 
  signal err_OBUF_GROM : STD_LOGIC; 
  signal Q_n0019_2_FROM : STD_LOGIC; 
  signal Q_n0019_2_GROM : STD_LOGIC; 
  signal Q_n0019_3_FROM : STD_LOGIC; 
  signal Q_n0019_3_GROM : STD_LOGIC; 
  signal CHOICE21_FROM : STD_LOGIC; 
  signal CHOICE21_GROM : STD_LOGIC; 
  signal Msub_n0009_inst_lut2_18_FROM : STD_LOGIC; 
  signal Msub_n0009_inst_lut2_18_GROM : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal Q_n0015 : STD_LOGIC_VECTOR ( 7 downto 4 ); 
  signal Q_n0019 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Q_n0021 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal Q_n0016 : STD_LOGIC_VECTOR ( 7 downto 4 ); 
  signal Q_n0014 : STD_LOGIC_VECTOR ( 7 downto 4 ); 
  signal Q_n0013 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  err_OBUF_8 : X_TRI
    port map (
      I => err_OUTMUX,
      CTL => err_ENABLE,
      O => err
    );
  err_ENABLEINV : X_INV
    port map (
      I => err_TORGTS,
      O => err_ENABLE
    );
  err_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => err_TORGTS
    );
  err_OUTMUX_9 : X_BUF
    port map (
      I => err_OBUF,
      O => err_OUTMUX
    );
  y_0_OBUF_10 : X_TRI
    port map (
      I => y_0_OUTMUX,
      CTL => y_0_ENABLE,
      O => y(0)
    );
  y_0_ENABLEINV : X_INV
    port map (
      I => y_0_TORGTS,
      O => y_0_ENABLE
    );
  y_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => y_0_TORGTS
    );
  y_0_OUTMUX_11 : X_BUF
    port map (
      I => y_0_OBUF,
      O => y_0_OUTMUX
    );
  y_1_OBUF : X_TRI
    port map (
      I => y_1_OUTMUX,
      CTL => y_1_ENABLE,
      O => y(1)
    );
  y_1_ENABLEINV : X_INV
    port map (
      I => y_1_TORGTS,
      O => y_1_ENABLE
    );
  y_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => y_1_TORGTS
    );
  y_1_OUTMUX_12 : X_BUF
    port map (
      I => y_1_ODNOT,
      O => y_1_OUTMUX
    );
  y_1_OMUX : X_INV
    port map (
      I => Mcompar_n0007_inst_cy_17,
      O => y_1_ODNOT
    );
  y_2_OBUF : X_TRI
    port map (
      I => y_2_OUTMUX,
      CTL => y_2_ENABLE,
      O => y(2)
    );
  y_2_ENABLEINV : X_INV
    port map (
      I => y_2_TORGTS,
      O => y_2_ENABLE
    );
  y_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => y_2_TORGTS
    );
  y_2_OUTMUX_13 : X_BUF
    port map (
      I => y_2_ODNOT,
      O => y_2_OUTMUX
    );
  y_2_OMUX : X_INV
    port map (
      I => Mcompar_n0006_inst_cy_12,
      O => y_2_ODNOT
    );
  rest_0_OBUF_14 : X_TRI
    port map (
      I => rest_0_OUTMUX,
      CTL => rest_0_ENABLE,
      O => rest(0)
    );
  rest_0_ENABLEINV : X_INV
    port map (
      I => rest_0_TORGTS,
      O => rest_0_ENABLE
    );
  rest_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => rest_0_TORGTS
    );
  rest_0_OUTMUX_15 : X_BUF
    port map (
      I => rest_0_OBUF,
      O => rest_0_OUTMUX
    );
  y_3_OBUF : X_TRI
    port map (
      I => y_3_OUTMUX,
      CTL => y_3_ENABLE,
      O => y(3)
    );
  y_3_ENABLEINV : X_INV
    port map (
      I => y_3_TORGTS,
      O => y_3_ENABLE
    );
  y_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => y_3_TORGTS
    );
  y_3_OUTMUX_16 : X_BUF
    port map (
      I => y_3_ODNOT,
      O => y_3_OUTMUX
    );
  y_3_OMUX : X_INV
    port map (
      I => Mcompar_n0005_inst_cy_6,
      O => y_3_ODNOT
    );
  rest_1_OBUF_17 : X_TRI
    port map (
      I => rest_1_OUTMUX,
      CTL => rest_1_ENABLE,
      O => rest(1)
    );
  rest_1_ENABLEINV : X_INV
    port map (
      I => rest_1_TORGTS,
      O => rest_1_ENABLE
    );
  rest_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => rest_1_TORGTS
    );
  rest_1_OUTMUX_18 : X_BUF
    port map (
      I => rest_1_OBUF,
      O => rest_1_OUTMUX
    );
  rest_2_OBUF_19 : X_TRI
    port map (
      I => rest_2_OUTMUX,
      CTL => rest_2_ENABLE,
      O => rest(2)
    );
  rest_2_ENABLEINV : X_INV
    port map (
      I => rest_2_TORGTS,
      O => rest_2_ENABLE
    );
  rest_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => rest_2_TORGTS
    );
  rest_2_OUTMUX_20 : X_BUF
    port map (
      I => rest_2_OBUF,
      O => rest_2_OUTMUX
    );
  a_0_IMUX : X_BUF
    port map (
      I => a_0_IBUF_0,
      O => a_0_IBUF
    );
  a_0_IBUF_21 : X_BUF
    port map (
      I => a(0),
      O => a_0_IBUF_0
    );
  rest_3_OBUF_22 : X_TRI
    port map (
      I => rest_3_OUTMUX,
      CTL => rest_3_ENABLE,
      O => rest(3)
    );
  rest_3_ENABLEINV : X_INV
    port map (
      I => rest_3_TORGTS,
      O => rest_3_ENABLE
    );
  rest_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => rest_3_TORGTS
    );
  rest_3_OUTMUX_23 : X_BUF
    port map (
      I => rest_3_OBUF,
      O => rest_3_OUTMUX
    );
  a_1_IMUX : X_BUF
    port map (
      I => a_1_IBUF_1,
      O => a_1_IBUF
    );
  a_1_IBUF_24 : X_BUF
    port map (
      I => a(1),
      O => a_1_IBUF_1
    );
  a_2_IMUX : X_BUF
    port map (
      I => a_2_IBUF_2,
      O => a_2_IBUF
    );
  a_2_IBUF_25 : X_BUF
    port map (
      I => a(2),
      O => a_2_IBUF_2
    );
  a_3_IMUX : X_BUF
    port map (
      I => a_3_IBUF_3,
      O => a_3_IBUF
    );
  a_3_IBUF_26 : X_BUF
    port map (
      I => a(3),
      O => a_3_IBUF_3
    );
  b_0_IMUX : X_BUF
    port map (
      I => b_0_IBUF_4,
      O => b_0_IBUF
    );
  b_0_IBUF_27 : X_BUF
    port map (
      I => b(0),
      O => b_0_IBUF_4
    );
  b_1_IMUX : X_BUF
    port map (
      I => b_1_IBUF_5,
      O => b_1_IBUF
    );
  b_1_IBUF_28 : X_BUF
    port map (
      I => b(1),
      O => b_1_IBUF_5
    );
  b_2_IMUX : X_BUF
    port map (
      I => b_2_IBUF_6,
      O => b_2_IBUF
    );
  b_2_IBUF_29 : X_BUF
    port map (
      I => b(2),
      O => b_2_IBUF_6
    );
  b_3_IMUX : X_BUF
    port map (
      I => b_3_IBUF_7,
      O => b_3_IBUF
    );
  b_3_IBUF_30 : X_BUF
    port map (
      I => b(3),
      O => b_3_IBUF_7
    );
  Mcompar_n0005_inst_cy_4_LOGIC_ZERO_31 : X_ZERO
    port map (
      O => Mcompar_n0005_inst_cy_4_LOGIC_ZERO
    );
  Mcompar_n0005_inst_cy_3_32 : X_MUX2
    port map (
      IA => b_0_IBUF,
      IB => Mcompar_n0005_inst_cy_4_LOGIC_ZERO,
      SEL => Mcompar_n0005_inst_lut2_3,
      O => Mcompar_n0005_inst_cy_3
    );
  Mcompar_n0005_inst_lut2_31 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => b_0_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => a_3_IBUF,
      O => Mcompar_n0005_inst_lut2_3
    );
  Mcompar_n0005_inst_lut2_411 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => b_1_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_n0005_inst_lut2_4
    );
  Mcompar_n0005_inst_cy_4_COUTUSED : X_BUF
    port map (
      I => Mcompar_n0005_inst_cy_4_CYMUXG,
      O => Mcompar_n0005_inst_cy_4
    );
  Mcompar_n0005_inst_cy_4_33 : X_MUX2
    port map (
      IA => b_1_IBUF,
      IB => Mcompar_n0005_inst_cy_3,
      SEL => Mcompar_n0005_inst_lut2_4,
      O => Mcompar_n0005_inst_cy_4_CYMUXG
    );
  Mcompar_n0005_inst_cy_5_34 : X_MUX2
    port map (
      IA => b_2_IBUF,
      IB => Mcompar_n0005_inst_cy_6_CYINIT,
      SEL => Mcompar_n0005_inst_lut2_5,
      O => Mcompar_n0005_inst_cy_5
    );
  Mcompar_n0005_inst_lut2_511 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => b_2_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_n0005_inst_lut2_5
    );
  Mcompar_n0005_inst_lut2_611 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => b_3_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => Mcompar_n0005_inst_lut2_6
    );