xdeled.vhd

来自「24秒倒计时系统（有跑马灯） 利用CPLD」· VHDL 代码 · 共 53 行

library IEEE;
use IEEE.std_logic_1164.all;
entity xdeled is
    port (
        d_in: in STD_LOGIC_VECTOR (3 downto 0);
        a: out STD_LOGIC;
        b: out STD_LOGIC;
        c: out STD_LOGIC;
        d: out STD_LOGIC;
        e: out STD_LOGIC;
        f: out STD_LOGIC;
        g: out STD_LOGIC
         );
end xdeled;

architecture xdeled of xdeled is

begin 
  -- <<enter your statements here>>
process(d_in)
type data_out is array(0 to 6) of std_logic;
variable outp: data_out;
begin
 case d_in is
   when "0000" => outp := "1111110";
   when "0001" => outp := "0110000";
   when "0010" => outp := "1101101";
   when "0011" => outp := "1111001";
   when "0100" => outp := "0110011";
   when "0101" => outp := "1011011";
   when "0110" => outp := "1011111";
   when "0111" => outp := "1110000";
   when "1000" => outp := "1111111";
   when "1001" => outp := "1111011";
   when "1010" => outp := "1110111";
   when "1011" => outp := "0011111";
   when "1100" => outp := "1001110";
   when "1101" => outp := "0111101";
   when "1110" => outp := "1001111";
   when "1111" => outp := "1000111";
   when others => null;
 end case;
  a <= outp(0);
  b <= outp(1);
  c <= outp(2);
  d <= outp(3);
  e <= outp(4);
  f <= outp(5);
  g <= outp(6);
end process;
end xdeled;