fen20.vhd

来自「24秒倒计时系统（有跑马灯） 利用CPLD」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;

entity fen20 is 
generic(n:integer:=19);
port
(clk:in std_logic;
 clk5hz:out std_logic
);
end;


architecture behavior of fen20 is
signal counter:integer range 0 to 19;
signal clk1:std_logic;
begin 
process(clk)
begin
if rising_edge(clk) then
   if counter=19 then 
      clk1<=not clk1;
      counter<=0;
   else
   counter<=counter+1;
   end if;
end if;
end process;
clk5hz<=clk1;
end;