fen100.vhd

24秒倒计时系统（有跑马灯） 利用CPLD

library ieee;
use ieee.std_logic_1164.all;

entity fen100 is 
generic(n:integer:=49);
port
(clk:in std_logic;
 clk100hz:out std_logic
);
end;


architecture behavior of fen100 is
signal counter:integer range 0 to 49;
signal clk1:std_logic;
begin 
process(clk)
begin
if rising_edge(clk) then
   if counter=49 then 
      clk1<=not clk1;
      counter<=0;
   else
   counter<=counter+1;
   end if;
end if;
end process;
clk100hz<=clk1;
end;