complementor.vhd

用VHDL写的计算器

library ieee;
use ieee.std_logic_1164.all;

entity Complementor is
port(num: in std_logic_vector(3 downto 0);
     numout: out std_logic_vector(3 downto 0));
end entity;

architecture Impl of Complementor is
  component F4a_adder
	port(a, b: in std_logic_vector(3 downto 0);
    	s: out std_logic_vector(3 downto 0);
   		carry: out std_logic );
  end component;
signal Inverse, one:std_logic_vector(3 downto 0);
begin
  one(0)<='1';
  one(1)<='0';
  one(2)<='0';
  one(3)<='0';
  Inverse(0)<=not num(0);Inverse(1)<=not num(1);Inverse(2)<=not num(2);Inverse(3)<=not num(3);
  u: F4a_adder port map
    (a=>Inverse, b=>one, s=>numout); 
end architecture Impl;