ivga.fit.eqn

用VHDL写的计算器

--H2L1 is cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u2|cout~12 at LC_X7_Y15_N1
--operation mode is normal

H2L1 = B1_vb[1] & (B1_va[1] # B1_va[0] & B1_vb[0]) # !B1_vb[1] & B1_va[0] & B1_vb[0] & B1_va[1];


--H7L1 is cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u3|cout~92 at LC_X7_Y15_N8
--operation mode is normal

H7L1 = H2L2 # B1_va[2] $ B1_vb[2] $ H2L1;


--H3L1 is cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u3|cout~77 at LC_X7_Y15_N4
--operation mode is normal

H3L1 = B1_va[2] & (B1_vb[2] # H2L1) # !B1_va[2] & B1_vb[2] & (H2L1);


--B1_va[3] is cal:u1|va[3] at LC_X6_Y17_N5
--operation mode is normal

B1_va[3]_lut_out = DATA[3] # !En & !B1_STX.st0;
B1_va[3] = DFFEAS(B1_va[3]_lut_out, GLOBAL(clk_vga), VCC, , B1L23, , , , );


--B1_vb[3] is cal:u1|vb[3] at LC_X6_Y17_N2
--operation mode is normal

B1_vb[3]_lut_out = DATA[3] # !En & B1_STX.st2;
B1_vb[3] = DFFEAS(B1_vb[3]_lut_out, GLOBAL(clk_vga), VCC, , B1L93, , , , );


--E1L1 is cal:u1|bcd:u1|BCD4Adder:ua|six[2]~211 at LC_X7_Y15_N2
--operation mode is normal

E1L1 = B1_va[3] & (H3L1 # H7L1 # B1_vb[3]) # !B1_va[3] & (H3L1 & (H7L1 # B1_vb[3]) # !H3L1 & H7L1 & B1_vb[3]);


--B1_opin is cal:u1|opin at LC_X7_Y16_N2
--operation mode is normal

B1_opin_lut_out = B1L3 & (DATA[0]) # !B1L3 & B1_opin;
B1_opin = DFFEAS(B1_opin_lut_out, GLOBAL(clk_vga), VCC, , B1L21, , , , );


--B1_op[0] is cal:u1|op[0] at LC_X6_Y16_N8
--operation mode is normal

B1_op[0]_lut_out = DATA[0] # !B1L3 & B1_STX.st1;
B1_op[0] = DFFEAS(B1_op[0]_lut_out, GLOBAL(clk_vga), VCC, , B1L6, , , , );


--B1_STX.st1 is cal:u1|STX.st1 at LC_X5_Y16_N3
--operation mode is normal

B1_STX.st1_lut_out = B1L42 & (!B1L3 # !B1_STX.st1);
B1_STX.st1 = DFFEAS(B1_STX.st1_lut_out, GLOBAL(clk_vga), !GLOBAL(reset), , , , , , );


--B1_STX.st0 is cal:u1|STX.st0 at LC_X5_Y16_N0
--operation mode is normal

B1_STX.st0_lut_out = !B1L02 & (B1_STX.st0 # !B1L2);
B1_STX.st0 = DFFEAS(B1_STX.st0_lut_out, GLOBAL(clk_vga), !GLOBAL(reset), , , , , , );


--H11L1 is cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u|f_adder:u3|cout~1 at LC_X5_Y15_N7
--operation mode is normal

H11L1 = B1_vb[1] # B1_vb[0] # B1_vb[2];


--H41L1 is cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u2|cout~3 at LC_X6_Y15_N8
--operation mode is normal

H41L1 = B1_vb[1] # !B1_vb[0] # !B1_va[0];


--H41L2 is cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u2|cout~110 at LC_X6_Y15_N1
--operation mode is normal

H41L2 = B1_va[1] & (B1_vb[1] & (B1_va[0] # !B1_vb[0]) # !B1_vb[1] & (B1_vb[0]));


--H11_sum is cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u|f_adder:u3|sum at LC_X6_Y15_N9
--operation mode is normal

H11_sum = B1_vb[2] $ (B1_vb[1] # B1_vb[0]);


--H51L1 is cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u3|cout~13 at LC_X6_Y15_N6
--operation mode is normal

H51L1 = H11_sum & (B1_va[2] # H41L2 # !H41L1) # !H11_sum & B1_va[2] & (H41L2 # !H41L1);


--H61L1 is cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u4|cout~13 at LC_X6_Y14_N7
--operation mode is normal

H61L1 = B1_va[3] & (H51L1 # B1_vb[3] $ H11L1) # !B1_va[3] & H51L1 & (B1_vb[3] $ H11L1);


--B1L31 is cal:u1|Q[1]~1244 at LC_X5_Y15_N2
--operation mode is normal

B1L31 = H2L2 $ (H61L1 & B1_vb[0] # !H61L1 & (B1_va[0]));


--H6L1 is cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u2|sum~0 at LC_X7_Y15_N3
--operation mode is normal

H6L1 = E1L1 $ H2L2;


--B1_op[1] is cal:u1|op[1] at LC_X5_Y16_N7
--operation mode is normal

B1_op[1]_lut_out = B1_STX.st1 # DATA[1];
B1_op[1] = DFFEAS(B1_op[1]_lut_out, GLOBAL(clk_vga), VCC, , B1L6, , , , );


--C1_vga_data[2] is VgaInterface:u2|vga_data[2] at LC_X7_Y15_N7
--operation mode is normal

C1_vga_data[2]_lut_out = B1L51 # B1L41 # H91_sum & D1L1;
C1_vga_data[2] = DFFEAS(C1_vga_data[2]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_data[14] is VgaInterface:u2|vga_data[14] at LC_X6_Y14_N9
--operation mode is normal

C1_vga_data[14]_lut_out = B1_vb[2] # !B1_STX.st4 & !B1_STX.st3;
C1_vga_data[14] = DFFEAS(C1_vga_data[14]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_data[11] is VgaInterface:u2|vga_data[11] at LC_X6_Y14_N3
--operation mode is normal

C1_vga_data[11]_lut_out = VCC;
C1_vga_data[11] = DFFEAS(C1_vga_data[11]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1L15 is VgaInterface:u2|char_address~664 at LC_X6_Y14_N1
--operation mode is normal

C1L15 = C1L54 & (C1L34 # C1_vga_data[14]) # !C1L54 & !C1L34 & (C1_vga_data[11]);


--C1L25 is VgaInterface:u2|char_address~665 at LC_X6_Y14_N2
--operation mode is normal

C1L25 = C1L15 & (C1_vga_data[7] # !C1L34) # !C1L15 & (C1L34 & C1_vga_data[2]);


--C1_vga_data[18] is VgaInterface:u2|vga_data[18] at LC_X6_Y16_N6
--operation mode is normal

C1_vga_data[18]_lut_out = B1_STX.st1 # B1_op[2] # !B1_STX.st0;
C1_vga_data[18] = DFFEAS(C1_vga_data[18]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_data[22] is VgaInterface:u2|vga_data[22] at LC_X5_Y14_N8
--operation mode is normal

C1_vga_data[22]_lut_out = B1_va[2] # !B1_STX.st0;
C1_vga_data[22] = DFFEAS(C1_vga_data[22]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_data[15] is VgaInterface:u2|vga_data[15] at LC_X7_Y16_N8
--operation mode is normal

C1_vga_data[15]_lut_out = B1_vb[3] # !B1_STX.st3 & !B1_STX.st4;
C1_vga_data[15] = DFFEAS(C1_vga_data[15]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_data[3] is VgaInterface:u2|vga_data[3] at LC_X6_Y15_N4
--operation mode is normal

C1_vga_data[3]_lut_out = B1L71 # B1L61 # !B1_opin & H8_sum;
C1_vga_data[3] = DFFEAS(C1_vga_data[3]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1L35 is VgaInterface:u2|char_address~666 at LC_X6_Y14_N5
--operation mode is normal

C1L35 = C1L54 & (C1L34) # !C1L54 & (C1L34 & (C1_vga_data[3]) # !C1L34 & C1_vga_data[11]);


--C1L45 is VgaInterface:u2|char_address~667 at LC_X6_Y14_N6
--operation mode is normal

C1L45 = C1L54 & (C1L35 & (C1_vga_data[7]) # !C1L35 & C1_vga_data[15]) # !C1L54 & (C1L35);


--C1_vga_data[19] is VgaInterface:u2|vga_data[19] at LC_X6_Y16_N0
--operation mode is normal

C1_vga_data[19]_lut_out = B1_STX.st1 # B1_op[3] # !B1_STX.st0;
C1_vga_data[19] = DFFEAS(C1_vga_data[19]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_data[23] is VgaInterface:u2|vga_data[23] at LC_X5_Y14_N0
--operation mode is normal

C1_vga_data[23]_lut_out = B1_va[3] # !B1_STX.st0;
C1_vga_data[23] = DFFEAS(C1_vga_data[23]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--B1_STX.st2 is cal:u1|STX.st2 at LC_X5_Y16_N6
--operation mode is normal

B1_STX.st2_lut_out = !B1L91 & !B1L02 & (B1L12 # B1L04);
B1_STX.st2 = DFFEAS(B1_STX.st2_lut_out, GLOBAL(clk_vga), !GLOBAL(reset), , , , , , );


--B1L2 is cal:u1|COMREG~177 at LC_X5_Y17_N7
--operation mode is normal

B1L2 = DATA[3] & (DATA[2] # DATA[1]) # !En;


--B1L3 is cal:u1|COMREG~178 at LC_X5_Y17_N8
--operation mode is normal

B1L3 = !DATA[2] & DATA[3] & En & DATA[1];


--B1L83 is cal:u1|vb[0]~338 at LC_X5_Y16_N5
--operation mode is normal

B1L83 = B1L3 # !B1_STX.st2;


--B1L93 is cal:u1|vb[0]~339 at LC_X5_Y16_N4
--operation mode is normal

B1L93 = !reset & (!B1L2 & B1_STX.st3 # !B1L83);


--B1L81 is cal:u1|Select~1042 at LC_X5_Y17_N3
--operation mode is normal

B1L81 = DATA[2] & DATA[3] & En & !DATA[1];


--B1L91 is cal:u1|Select~1043 at LC_X5_Y17_N6
--operation mode is normal

B1L91 = !DATA[0] & (B1_STX.st3 & B1L81);


--B1L02 is cal:u1|Select~1044 at LC_X5_Y17_N4
--operation mode is normal

B1_STX.st4_qfbk = B1_STX.st4;
B1L02 = DATA[0] & (B1_STX.st4_qfbk & B1L81);

--B1_STX.st4 is cal:u1|STX.st4 at LC_X5_Y17_N4
--operation mode is normal

B1_STX.st4 = DFFEAS(B1L02, GLOBAL(clk_vga), !GLOBAL(reset), , B1L32, B1L91, , , VCC);


--B1L12 is cal:u1|Select~1045 at LC_X5_Y17_N9
--operation mode is normal

B1L12 = B1L3 & B1_STX.st1;


--B1L22 is cal:u1|Select~1046 at LC_X5_Y17_N5
--operation mode is normal

B1L22 = !B1L2 & (B1_STX.st2 # !B1_STX.st0);


--B1L32 is cal:u1|Select~1047 at LC_X5_Y17_N2
--operation mode is normal

B1L32 = B1L12 # B1L02 # B1L91 # B1L22;


--B1L1 is cal:u1|COMREG~5 at LC_X5_Y17_N0
--operation mode is normal

B1L1 = !DATA[0] & (B1L81);


--B1L23 is cal:u1|va[0]~275 at LC_X5_Y16_N9
--operation mode is normal

B1L23 = !reset & (B1_STX.st1 & (!B1L2) # !B1_STX.st1 & !B1_STX.st0);


--B1L21 is cal:u1|opin~177 at LC_X6_Y16_N5
--operation mode is normal

B1L21 = !reset & (B1_STX.st2 & B1L2 # !B1_STX.st2 & (B1_STX.st1));


--B1L9 is cal:u1|op[2]~207 at LC_X5_Y16_N2
--operation mode is normal

B1L9 = !B1_STX.st1 # !B1L2;


--B1L6 is cal:u1|op[0]~208 at LC_X5_Y16_N8
--operation mode is normal

B1L6 = !reset & (B1_STX.st2 & B1L3 # !B1L9);


--B1L42 is cal:u1|Select~1057 at LC_X5_Y16_N1
--operation mode is normal

B1L42 = B1L2 & (B1_STX.st1) # !B1L2 & !B1_STX.st2 & (B1_STX.st1 # !B1_STX.st0);


--H3L2 is cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u3|sum~24 at LC_X5_Y15_N4
--operation mode is normal

H3L2 = B1_vb[2] $ H2L1 $ B1_va[2];


--B1L41 is cal:u1|Q[2]~1250 at LC_X7_Y15_N6
--operation mode is normal

B1L41 = !B1_opin & (H3L2 $ (E1L1 & !H2L2));


--H51_sum is cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u3|sum at LC_X5_Y15_N8
--operation mode is normal

H51_sum = H11_sum $ B1_va[2] $ (H41L2 # !H41L1);


--B1L51 is cal:u1|Q[2]~1251 at LC_X7_Y15_N9
--operation mode is normal

B1L51 = H51_sum & H61L1 & B1_opin # !B1_STX.st4;


--D1L1 is cal:u1|bcd:u1|sum[7]~21 at LC_X7_Y15_N5
--operation mode is normal

D1L1 = !H61L1 & B1_opin;


--H81L1 is cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u|f_adder:u2|cout~1 at LC_X5_Y15_N5
--operation mode is normal

H81L1 = B1_vb[0] & (B1_vb[1] $ B1_va[1] # !B1_va[0]) # !B1_vb[0] & (B1_va[0] # B1_vb[1] $ B1_va[1]);


--H91_sum is cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u|f_adder:u3|sum at LC_X5_Y15_N9
--operation mode is normal

H91_sum = H51_sum $ H81L1;


--B1_op[2] is cal:u1|op[2] at LC_X6_Y16_N4
--operation mode is normal

B1_op[2]_lut_out = DATA[2] # B1_STX.st1 & !B1L3;
B1_op[2] = DFFEAS(B1_op[2]_lut_out, GLOBAL(clk_vga), VCC, , B1L6, , , , );


--H61_sum is cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u4|sum at LC_X6_Y15_N3
--operation mode is normal

H61_sum = B1_vb[3] $ H11L1 $ B1_va[3] $ H51L1;


--B1L61 is cal:u1|Q[3]~1257 at LC_X6_Y15_N2
--operation mode is normal

B1L61 = D1L1 & (H61_sum $ (H51_sum # H81L1));


--B1L71 is cal:u1|Q[3]~1258 at LC_X6_Y15_N5
--operation mode is normal

B1L71 = B1_opin & H61_sum & H61L1 # !B1_STX.st4;


--H8_sum is cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u4|sum at LC_X6_Y17_N4
--operation mode is normal

H8_sum = H7L1 & (B1_va[3] & (B1_vb[3] $ H3L1) # !B1_va[3] & B1_vb[3] & H3L1) # !H7L1 & (B1_va[3] $ B1_vb[3] $ H3L1);


--B1_op[3] is cal:u1|op[3] at LC_X6_Y16_N3
--operation mode is normal

B1_op[3]_lut_out = DATA[3] # B1_STX.st1;
B1_op[3] = DFFEAS(B1_op[3]_lut_out, GLOBAL(clk_vga), VCC, , B1L6, , , , );


--B1L04 is cal:u1|vb[0]~340 at LC_X6_Y17_N0
--operation mode is normal

B1L04 = B1L2 & B1_STX.st2;


--reset is reset at PIN_239
--operation mode is input

reset = INPUT();


--clk_vga is clk_vga at PIN_152
--operation mode is input

clk_vga = INPUT();


--DATA[0] is DATA[0] at PIN_233
--operation mode is input

DATA[0] = INPUT();


--DATA[3] is DATA[3] at PIN_236
--operation mode is input

DATA[3] = INPUT();


--DATA[1] is DATA[1] at PIN_234
--operation mode is input

DATA[1] = INPUT();


--DATA[2] is DATA[2] at PIN_235
--operation mode is input

DATA[2] = INPUT();


--En is En at PIN_240
--operation mode is input

En = INPUT();


--Ovga_r is Ovga_r at PIN_226
--operation mode is output

Ovga_r = OUTPUT(C1_pod_vga_r);


--Ovga_g is Ovga_g at PIN_225
--operation mode is output

Ovga_g = OUTPUT(C1_pod_vga_r);


--Ovga_b is Ovga_b at PIN_223
--operation mode is output

Ovga_b = OUTPUT(C1_pod_vga_r);


--Ovga_hs is Ovga_hs at PIN_222
--operation mode is output

Ovga_hs = OUTPUT(C1_pod_vga_hs);


--Ovga_vs is Ovga_vs at PIN_219
--operation mode is output

Ovga_vs = OUTPUT(C1_pod_vga_vs);