ivga.fit.eqn

用VHDL写的计算器

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--C1_pod_vga_r is VgaInterface:u2|pod_vga_r at LC_X11_Y14_N8
--operation mode is normal

C1_pod_vga_r_lut_out = C1_enable & (C1_vga_r);
C1_pod_vga_r = DFFEAS(C1_pod_vga_r_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_pod_vga_hs is VgaInterface:u2|pod_vga_hs at LC_X10_Y15_N2
--operation mode is normal

C1_pod_vga_hs_lut_out = !C1_hs_p;
C1_pod_vga_hs = DFFEAS(C1_pod_vga_hs_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_pod_vga_vs is VgaInterface:u2|pod_vga_vs at LC_X11_Y14_N0
--operation mode is normal

C1_pod_vga_vs_lut_out = !C1_vs_p;
C1_pod_vga_vs = DFFEAS(C1_pod_vga_vs_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vga_r is VgaInterface:u2|vga_r at LC_X11_Y14_N7
--operation mode is normal

C1_vga_r_lut_out = M1_address_reg_a[4] & (N1L1 & M1_ram_block1a3 # !N1L1 & (M1_ram_block1a1)) # !M1_address_reg_a[4] & (N1L1);
C1_vga_r = DFFEAS(C1_vga_r_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_enable is VgaInterface:u2|enable at LC_X11_Y14_N2
--operation mode is normal

C1_enable_lut_out = !C1L121 & (!C1_vector_x[7] & !C1_vector_x[8] # !C1_vector_x[9]);
C1_enable = DFFEAS(C1_enable_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_clk is VgaInterface:u2|clk at LC_X8_Y10_N2
--operation mode is normal

C1_clk_lut_out = !C1_clk;
C1_clk = DFFEAS(C1_clk_lut_out, GLOBAL(clk_vga), VCC, , , , , , );


--C1_hs_p is VgaInterface:u2|hs_p at LC_X10_Y13_N8
--operation mode is normal

C1_hs_p_lut_out = !C1_vector_x[8] & C1_vector_x[9] & C1_vector_x[7] & C1L97;
C1_hs_p = DFFEAS(C1_hs_p_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vs_p is VgaInterface:u2|vs_p at LC_X11_Y14_N6
--operation mode is normal

C1_vs_p_lut_out = C1_vector_y[1] & C1_vector_y[3] & C1L85 & C1L121;
C1_vs_p = DFFEAS(C1_vs_p_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--M1_ram_block1a1 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a1 at M4K_X17_Y15
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a1_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a1_PORT_A_address_reg = DFFE(M1_ram_block1a1_PORT_A_address, M1_ram_block1a1_clock_0, , , );
M1_ram_block1a1_clock_0 = GLOBAL(C1_clk);
M1_ram_block1a1_PORT_A_data_out = MEMORY(, , M1_ram_block1a1_PORT_A_address_reg, , , , , , M1_ram_block1a1_clock_0, , , , , );
M1_ram_block1a1_PORT_A_data_out_reg = DFFE(M1_ram_block1a1_PORT_A_data_out, M1_ram_block1a1_clock_0, , , );
M1_ram_block1a1 = M1_ram_block1a1_PORT_A_data_out_reg[0];


--M1_address_reg_a[4] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[4] at LC_X11_Y14_N3
--operation mode is normal

M1_address_reg_a[4]_lut_out = GND;
M1_address_reg_a[4] = DFFEAS(M1_address_reg_a[4]_lut_out, GLOBAL(C1_clk), VCC, , , M1_address_reg_a[0], , , VCC);


--M1_ram_block1a2 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a2 at M4K_X17_Y14
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a2_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a2_PORT_A_address_reg = DFFE(M1_ram_block1a2_PORT_A_address, M1_ram_block1a2_clock_0, , , );
M1_ram_block1a2_clock_0 = GLOBAL(C1_clk);
M1_ram_block1a2_PORT_A_data_out = MEMORY(, , M1_ram_block1a2_PORT_A_address_reg, , , , , , M1_ram_block1a2_clock_0, , , , , );
M1_ram_block1a2_PORT_A_data_out_reg = DFFE(M1_ram_block1a2_PORT_A_data_out, M1_ram_block1a2_clock_0, , , );
M1_ram_block1a2 = M1_ram_block1a2_PORT_A_data_out_reg[0];


--M1_ram_block1a0 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a0 at M4K_X17_Y13
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a0_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a0_PORT_A_address_reg = DFFE(M1_ram_block1a0_PORT_A_address, M1_ram_block1a0_clock_0, , , );
M1_ram_block1a0_clock_0 = GLOBAL(C1_clk);
M1_ram_block1a0_PORT_A_data_out = MEMORY(, , M1_ram_block1a0_PORT_A_address_reg, , , , , , M1_ram_block1a0_clock_0, , , , , );
M1_ram_block1a0_PORT_A_data_out_reg = DFFE(M1_ram_block1a0_PORT_A_data_out, M1_ram_block1a0_clock_0, , , );
M1_ram_block1a0 = M1_ram_block1a0_PORT_A_data_out_reg[0];


--N1L1 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|mux_gcb:mux2|w_result148w~44 at LC_X11_Y14_N1
--operation mode is normal

M1_address_reg_a[5]_qfbk = M1_address_reg_a[5];
N1L1 = M1_address_reg_a[4] & (M1_address_reg_a[5]_qfbk) # !M1_address_reg_a[4] & (M1_address_reg_a[5]_qfbk & M1_ram_block1a2 # !M1_address_reg_a[5]_qfbk & (M1_ram_block1a0));

--M1_address_reg_a[5] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[5] at LC_X11_Y14_N1
--operation mode is normal

M1_address_reg_a[5] = DFFEAS(N1L1, GLOBAL(C1_clk), VCC, , , M1_address_reg_a[1], , , VCC);


--M1_ram_block1a3 is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|ram_block1a3 at M4K_X17_Y12
--RAM Block Operation Mode: ROM
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 65536, Port A Logical Width: 1
--Port A Input: Registered, Port A Output: Registered
M1_ram_block1a3_PORT_A_address = BUS(C1_char_address[0], C1_char_address[1], C1_char_address[2], C1_char_address[3], C1_char_address[4], C1_char_address[5], C1_char_address[6], C1_char_address[7], C1_char_address[8], C1_char_address[9], C1_char_address[10], C1_char_address[11]);
M1_ram_block1a3_PORT_A_address_reg = DFFE(M1_ram_block1a3_PORT_A_address, M1_ram_block1a3_clock_0, , , );
M1_ram_block1a3_clock_0 = GLOBAL(C1_clk);
M1_ram_block1a3_PORT_A_data_out = MEMORY(, , M1_ram_block1a3_PORT_A_address_reg, , , , , , M1_ram_block1a3_clock_0, , , , , );
M1_ram_block1a3_PORT_A_data_out_reg = DFFE(M1_ram_block1a3_PORT_A_data_out, M1_ram_block1a3_clock_0, , , );
M1_ram_block1a3 = M1_ram_block1a3_PORT_A_data_out_reg[0];


--C1_vector_y[5] is VgaInterface:u2|vector_y[5] at LC_X8_Y14_N5
--operation mode is arithmetic

C1_vector_y[5]_carry_eqn = (!C1L801 & GND) # (C1L801 & VCC);
C1_vector_y[5]_lut_out = C1_vector_y[5] $ C1_vector_y[5]_carry_eqn;
C1_vector_y[5] = DFFEAS(C1_vector_y[5]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L211 is VgaInterface:u2|vector_y[5]~206 at LC_X8_Y14_N5
--operation mode is arithmetic

C1L211_cout_0 = !C1L801 # !C1_vector_y[5];
C1L211 = CARRY(C1L211_cout_0);

--C1L311 is VgaInterface:u2|vector_y[5]~206COUT1_246 at LC_X8_Y14_N5
--operation mode is arithmetic

C1L311_cout_1 = !C1L801 # !C1_vector_y[5];
C1L311 = CARRY(C1L311_cout_1);


--C1_vector_y[7] is VgaInterface:u2|vector_y[7] at LC_X8_Y14_N7
--operation mode is arithmetic

C1_vector_y[7]_carry_eqn = (!C1L801 & C1L511) # (C1L801 & C1L611);
C1_vector_y[7]_lut_out = C1_vector_y[7] $ (C1_vector_y[7]_carry_eqn);
C1_vector_y[7] = DFFEAS(C1_vector_y[7]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L811 is VgaInterface:u2|vector_y[7]~210 at LC_X8_Y14_N7
--operation mode is arithmetic

C1L811_cout_0 = !C1L511 # !C1_vector_y[7];
C1L811 = CARRY(C1L811_cout_0);

--C1L911 is VgaInterface:u2|vector_y[7]~210COUT1_248 at LC_X8_Y14_N7
--operation mode is arithmetic

C1L911_cout_1 = !C1L611 # !C1_vector_y[7];
C1L911 = CARRY(C1L911_cout_1);


--C1_vector_y[6] is VgaInterface:u2|vector_y[6] at LC_X8_Y14_N6
--operation mode is arithmetic

C1_vector_y[6]_carry_eqn = (!C1L801 & C1L211) # (C1L801 & C1L311);
C1_vector_y[6]_lut_out = C1_vector_y[6] $ (!C1_vector_y[6]_carry_eqn);
C1_vector_y[6] = DFFEAS(C1_vector_y[6]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L511 is VgaInterface:u2|vector_y[6]~214 at LC_X8_Y14_N6
--operation mode is arithmetic

C1L511_cout_0 = C1_vector_y[6] & (!C1L211);
C1L511 = CARRY(C1L511_cout_0);

--C1L611 is VgaInterface:u2|vector_y[6]~214COUT1_247 at LC_X8_Y14_N6
--operation mode is arithmetic

C1L611_cout_1 = C1_vector_y[6] & (!C1L311);
C1L611 = CARRY(C1L611_cout_1);


--C1_vector_y[8] is VgaInterface:u2|vector_y[8] at LC_X8_Y14_N8
--operation mode is normal

C1_vector_y[8]_carry_eqn = (!C1L801 & C1L811) # (C1L801 & C1L911);
C1_vector_y[8]_lut_out = C1_vector_y[8] $ !C1_vector_y[8]_carry_eqn;
C1_vector_y[8] = DFFEAS(C1_vector_y[8]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );


--C1L121 is VgaInterface:u2|vector_y[8]~221 at LC_X11_Y14_N5
--operation mode is normal

C1L121 = C1_vector_y[8] & C1_vector_y[7] & C1_vector_y[5] & C1_vector_y[6];


--C1_vector_x[9] is VgaInterface:u2|vector_x[9] at LC_X10_Y13_N5
--operation mode is normal

C1_vector_x[9]_lut_out = C1L1 & (!C1L28);
C1_vector_x[9] = DFFEAS(C1_vector_x[9]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1_vector_x[8] is VgaInterface:u2|vector_x[8] at LC_X10_Y13_N9
--operation mode is normal

C1_vector_x[8]_lut_out = C1L2 & (!C1L28);
C1_vector_x[8] = DFFEAS(C1_vector_x[8]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1L56 is VgaInterface:u2|process4~710 at LC_X10_Y13_N3
--operation mode is normal

C1L56 = !C1_vector_x[8] & C1_vector_x[7];


--C1_vector_x[5] is VgaInterface:u2|vector_x[5] at LC_X9_Y13_N4
--operation mode is normal

C1_vector_x[5]_lut_out = C1L11 & (!C1L28);
C1_vector_x[5] = DFFEAS(C1_vector_x[5]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , , , , );


--C1L97 is VgaInterface:u2|process6~49 at LC_X10_Y13_N1
--operation mode is normal

C1L97 = C1_vector_x[5] & (!C1_vector_x[4] # !C1_vector_x[6]) # !C1_vector_x[5] & (C1_vector_x[6] # C1_vector_x[4]);


--C1_vector_y[1] is VgaInterface:u2|vector_y[1] at LC_X8_Y14_N1
--operation mode is arithmetic

C1_vector_y[1]_lut_out = C1_vector_y[1] $ (C1L69);
C1_vector_y[1] = DFFEAS(C1_vector_y[1]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L99 is VgaInterface:u2|vector_y[1]~223 at LC_X8_Y14_N1
--operation mode is arithmetic

C1L99_cout_0 = !C1L69 # !C1_vector_y[1];
C1L99 = CARRY(C1L99_cout_0);

--C1L001 is VgaInterface:u2|vector_y[1]~223COUT1_244 at LC_X8_Y14_N1
--operation mode is arithmetic

C1L001_cout_1 = !C1L79 # !C1_vector_y[1];
C1L001 = CARRY(C1L001_cout_1);


--C1_vector_y[3] is VgaInterface:u2|vector_y[3] at LC_X8_Y14_N3
--operation mode is arithmetic

C1_vector_y[3]_lut_out = C1_vector_y[3] $ C1L201;
C1_vector_y[3] = DFFEAS(C1_vector_y[3]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L501 is VgaInterface:u2|vector_y[3]~227 at LC_X8_Y14_N3
--operation mode is arithmetic

C1L501_cout_0 = !C1L201 # !C1_vector_y[3];
C1L501 = CARRY(C1L501_cout_0);

--C1L601 is VgaInterface:u2|vector_y[3]~227COUT1 at LC_X8_Y14_N3
--operation mode is arithmetic

C1L601_cout_1 = !C1L301 # !C1_vector_y[3];
C1L601 = CARRY(C1L601_cout_1);


--C1_vector_y[2] is VgaInterface:u2|vector_y[2] at LC_X8_Y14_N2
--operation mode is arithmetic

C1_vector_y[2]_lut_out = C1_vector_y[2] $ (!C1L99);
C1_vector_y[2] = DFFEAS(C1_vector_y[2]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L201 is VgaInterface:u2|vector_y[2]~231 at LC_X8_Y14_N2
--operation mode is arithmetic

C1L201_cout_0 = C1_vector_y[2] & (!C1L99);
C1L201 = CARRY(C1L201_cout_0);

--C1L301 is VgaInterface:u2|vector_y[2]~231COUT1_245 at LC_X8_Y14_N2
--operation mode is arithmetic

C1L301_cout_1 = C1_vector_y[2] & (!C1L001);
C1L301 = CARRY(C1L301_cout_1);


--C1_vector_y[4] is VgaInterface:u2|vector_y[4] at LC_X8_Y14_N4
--operation mode is arithmetic

C1_vector_y[4]_lut_out = C1_vector_y[4] $ !C1L501;
C1_vector_y[4] = DFFEAS(C1_vector_y[4]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , C1L28, , , , );

--C1L801 is VgaInterface:u2|vector_y[4]~235 at LC_X8_Y14_N4
--operation mode is arithmetic

C1L801 = C1L901;


--C1L85 is VgaInterface:u2|LessThan~1777 at LC_X11_Y14_N4
--operation mode is normal

C1L85 = !C1_vector_y[2] & !C1_vector_y[4];


--C1_char_address[0] is VgaInterface:u2|char_address[0] at LC_X10_Y14_N2
--operation mode is normal

C1_char_address[0]_lut_out = C1_vector_x[0] & (C1L17 # !C1L44);
C1_char_address[0] = DFFEAS(C1_char_address[0]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[1] is VgaInterface:u2|char_address[1] at LC_X10_Y14_N8
--operation mode is normal

C1_char_address[1]_lut_out = C1_vector_x[1] & (C1L17 # !C1L44);
C1_char_address[1] = DFFEAS(C1_char_address[1]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[2] is VgaInterface:u2|char_address[2] at LC_X10_Y14_N5
--operation mode is normal

C1_char_address[2]_lut_out = C1_vector_x[2] & (C1L17 # !C1L44);
C1_char_address[2] = DFFEAS(C1_char_address[2]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[3] is VgaInterface:u2|char_address[3] at LC_X10_Y14_N9
--operation mode is normal

C1_char_address[3]_lut_out = C1_vector_x[3] & (C1L17 # !C1L44);
C1_char_address[3] = DFFEAS(C1_char_address[3]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[4] is VgaInterface:u2|char_address[4] at LC_X10_Y14_N3
--operation mode is normal

C1_char_address[4]_lut_out = C1_vector_x[4] & (C1L17 # !C1L44);
C1_char_address[4] = DFFEAS(C1_char_address[4]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[5] is VgaInterface:u2|char_address[5] at LC_X10_Y14_N6
--operation mode is normal

C1_char_address[5]_lut_out = C1_vector_y[0] & (C1L17 # !C1L44);
C1_char_address[5] = DFFEAS(C1_char_address[5]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[6] is VgaInterface:u2|char_address[6] at LC_X10_Y14_N0
--operation mode is normal

C1_char_address[6]_lut_out = C1_vector_y[1] & (C1L17 # !C1L44);
C1_char_address[6] = DFFEAS(C1_char_address[6]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[7] is VgaInterface:u2|char_address[7] at LC_X10_Y14_N4
--operation mode is normal

C1_char_address[7]_lut_out = C1_vector_y[2] & (C1L17 # !C1L44);
C1_char_address[7] = DFFEAS(C1_char_address[7]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[8] is VgaInterface:u2|char_address[8] at LC_X10_Y14_N1
--operation mode is normal

C1_char_address[8]_lut_out = C1_vector_y[3] & (C1L17 # !C1L44);
C1_char_address[8] = DFFEAS(C1_char_address[8]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[9] is VgaInterface:u2|char_address[9] at LC_X10_Y14_N7
--operation mode is normal

C1_char_address[9]_lut_out = C1_vector_y[4] & (C1L17 # !C1L44);
C1_char_address[9] = DFFEAS(C1_char_address[9]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1_char_address[10] is VgaInterface:u2|char_address[10] at LC_X9_Y14_N4
--operation mode is normal

C1_char_address[10]_lut_out = C1L87 & (C1_vga_data[16]) # !C1L87 & C1L84;
C1_char_address[10] = DFFEAS(C1_char_address[10]_lut_out, GLOBAL(C1_clk), VCC, , , C1_vga_data[20], , C1L64, C1L67);


--C1_char_address[11] is VgaInterface:u2|char_address[11] at LC_X7_Y14_N4
--operation mode is normal

C1_char_address[11]_lut_out = C1L87 & C1_vga_data[17] # !C1L87 & (C1L05);
C1_char_address[11] = DFFEAS(C1_char_address[11]_lut_out, GLOBAL(C1_clk), VCC, , , C1_vga_data[21], , C1L64, C1L67);


--M1_address_reg_a[0] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[0] at LC_X11_Y14_N9
--operation mode is normal

M1_address_reg_a[0]_lut_out = C1_char_address[12];
M1_address_reg_a[0] = DFFEAS(M1_address_reg_a[0]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--M1_address_reg_a[1] is VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|address_reg_a[1] at LC_X8_Y13_N2
--operation mode is normal

M1_address_reg_a[1]_lut_out = C1_char_address[13];
M1_address_reg_a[1] = DFFEAS(M1_address_reg_a[1]_lut_out, GLOBAL(C1_clk), VCC, , , , , , );


--C1L08 is VgaInterface:u2|reduce_nor~48 at LC_X10_Y13_N4
--operation mode is normal

C1_vector_x[2]_qfbk = C1_vector_x[2];
C1L08 = C1_vector_x[5] # !C1_vector_x[4] # !C1_vector_x[2]_qfbk # !C1_vector_x[3];

--C1_vector_x[2] is VgaInterface:u2|vector_x[2] at LC_X10_Y13_N4
--operation mode is normal

C1_vector_x[2] = DFFEAS(C1L08, GLOBAL(C1_clk), !GLOBAL(reset), , , C1L91, , , VCC);


--C1_vector_x[0] is VgaInterface:u2|vector_x[0] at LC_X10_Y13_N0
--operation mode is normal

C1_vector_x[0]_lut_out = GND;
C1_vector_x[0] = DFFEAS(C1_vector_x[0]_lut_out, GLOBAL(C1_clk), !GLOBAL(reset), , , C1L52, , , VCC);


--C1L18 is VgaInterface:u2|reduce_nor~49 at LC_X10_Y13_N2
--operation mode is normal

C1_vector_x[1]_qfbk = C1_vector_x[1];
C1L18 = !C1_vector_x[0] # !C1_vector_x[1]_qfbk;

--C1_vector_x[1] is VgaInterface:u2|vector_x[1] at LC_X10_Y13_N2
--operation mode is normal

C1_vector_x[1] = DFFEAS(C1L18, GLOBAL(C1_clk), !GLOBAL(reset), , , C1L22, , , VCC);


--C1L66 is VgaInterface:u2|process4~711 at LC_X9_Y13_N5
--operation mode is normal

C1_vector_x[7]_qfbk = C1_vector_x[7];
C1L66 = !C1_vector_x[6] & !C1_vector_x[7]_qfbk & C1_vector_x[8];

--C1_vector_x[7] is VgaInterface:u2|vector_x[7] at LC_X9_Y13_N5
--operation mode is normal

C1_vector_x[7] = DFFEAS(C1L66, GLOBAL(C1_clk), !GLOBAL(reset), , , C1L5, , , VCC);


--C1L28 is VgaInterface:u2|reduce_nor~50 at LC_X10_Y13_N6
--operation mode is normal

C1L28 = !C1L18 & C1_vector_x[9] & !C1L08 & C1L66;


--C1L1 is VgaInterface:u2|add~242 at LC_X11_Y13_N9
--operation mode is normal

C1L1_carry_eqn = (!C1L51 & C1L3) # (C1L51 & C1L4);
C1L1 = C1_vector_x[9] $ C1L1_carry_eqn;


--C1L2 is VgaInterface:u2|add~247 at LC_X11_Y13_N8
--operation mode is arithmetic