bcd4suber.vhd

用VHDL写的计算器

library ieee;
use ieee.std_logic_1164.all;

entity BCD4suber is
port(Sa, Sb: in std_logic_vector(3 downto 0);
    Ss: out std_logic_vector(3 downto 0);
    Ssgn: out std_logic );
end entity;

architecture Impl of BCD4suber is
component F4a_adder is
port(a, b: in std_logic_vector(3 downto 0);
    s: out std_logic_vector(3 downto 0);
    carry: out std_logic );
end component;

component Complementor is
port(num: in std_logic_vector(3 downto 0);
     numout: out std_logic_vector(3 downto 0));
end component;

signal zero, tmpc, sgn: std_logic; 
signal tmp1, tmp2, tmp3: std_logic_vector(3 downto 0); 

begin
  zero<='0';
  u1: Complementor port map
    (num=>Sb, numout=>tmp1);    
  u2: F4a_adder port map
    (a=>Sa, b=>tmp1, s=>tmp2, carry=>tmpc); 
  sgn<=tmpc xor '1';
  u3: Complementor port map
    (num=>tmp2, numout=>tmp3); 
  Ssgn<=sgn;
  Ss(0)<=(tmp2(0) and (not sgn))or(tmp3(0) and sgn);
  Ss(1)<=(tmp2(1) and (not sgn))or(tmp3(1) and sgn);
  Ss(2)<=(tmp2(2) and (not sgn))or(tmp3(2) and sgn);
  Ss(3)<=(tmp2(3) and (not sgn))or(tmp3(3) and sgn);
  
end architecture Impl;