ivga.vhd

用VHDL写的计算器

library IEEE;
use IEEE.std_logic_1164.all;  
use IEEE.std_logic_unsigned.all;
entity Ivga is
Port( En                   :         in  std_logic;
      reset                :         in  STD_LOGIC;
      clk_vga              :         in  STD_LOGIC;
      DATA                 :         IN STD_LOGIC_vector(3 downto 0);
      Ovga_r               :         out STD_LOGIC;
      Ovga_g               :         out STD_LOGIC;
      Ovga_b               :         out STD_LOGIC;
      Ovga_hs              :         out STD_LOGIC;
      Ovga_vs              :         out STD_LOGIC
    );
end entity;
architecture beh of Ivga is
component VgaInterface
Port( reset                :         in  STD_LOGIC;
  clk_0                :         in  STD_LOGIC;
  ----  These are the Signals connect with CalControl
  pid_vga_data         :         in  STD_LOGIC_VECTOR(23 downto 0);
  ----  These are the VGA Control Signal
  pod_vga_r            :         out STD_LOGIC;
  pod_vga_g            :         out STD_LOGIC;
  pod_vga_b            :         out STD_LOGIC;
  pod_vga_hs           :         out STD_LOGIC;
  pod_vga_vs           :         out STD_LOGIC
);
end component;
component cal 
PORT ( 
         clk,reset,enable: in std_logic;
         DATAIN:           IN STD_LOGIC_vector(3 downto 0); 
         Q :               OUT STD_LOGIC_VECTOR(23 DOWNTO 0));
END component;
signal tempQ:   std_logic_vector(23 downto 0);
begin
u1:cal          port map(clk=>clk_vga,reset=>reset,DATAIN=>DATA,Q=>tempQ,enable=>EN);
u2:VgaInterface PORT MAP(reset=>reset,clk_0=>clk_vga,pid_vga_data=>tempQ,pod_vga_r=>Ovga_r,
    pod_vga_g=>Ovga_g,pod_vga_b=>Ovga_b,pod_vga_hs=>Ovga_hs,pod_vga_vs=>Ovga_vs);
end beh;