ivga.hif

用VHDL写的计算器

Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
32
1637
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
Ivga
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Ivga.vhd
1147322232
4
# storage
db|Ivga.(0).cnf
db|Ivga.(0).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
cal
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
cal.vhd
1147321969
4
# storage
db|Ivga.(1).cnf
db|Ivga.(1).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1
}
# end
# entity
bcd
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
bcd.vhd
1147322011
4
# storage
db|Ivga.(2).cnf
db|Ivga.(2).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1|bcd:u1
}
# end
# entity
BCD4Adder
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
bcd4adder.vhd
1147322026
4
# storage
db|Ivga.(3).cnf
db|Ivga.(3).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1|bcd:u1|BCD4Adder:ua
}
# end
# entity
F4a_adder
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
F4a_adder.vhd
1147322084
4
# storage
db|Ivga.(4).cnf
db|Ivga.(4).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2
cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u
cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2
cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u
}
# end
# entity
f_adder
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
f_adder.vhd
1147322106
4
# storage
db|Ivga.(5).cnf
db|Ivga.(5).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u1
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u2
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u3
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u1|f_adder:u4
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u1
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u2
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u3
cal:u1|bcd:u1|BCD4Adder:ua|F4a_adder:u2|f_adder:u4
cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u|f_adder:u1
cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u|f_adder:u2
cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u|f_adder:u3
cal:u1|bcd:u1|BCD4suber:us|Complementor:u1|F4a_adder:u|f_adder:u4
cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u1
cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u2
cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u3
cal:u1|bcd:u1|BCD4suber:us|F4a_adder:u2|f_adder:u4
cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u|f_adder:u1
cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u|f_adder:u2
cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u|f_adder:u3
cal:u1|bcd:u1|BCD4suber:us|Complementor:u3|F4a_adder:u|f_adder:u4
}
# end
# entity
BCD4suber
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
BCD4suber.vhd
1147322046
4
# storage
db|Ivga.(6).cnf
db|Ivga.(6).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1|bcd:u1|BCD4suber:us
}
# end
# entity
Complementor
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
Complementor.vhd
1147322068
4
# storage
db|Ivga.(7).cnf
db|Ivga.(7).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
cal:u1|bcd:u1|BCD4suber:us|Complementor:u1
cal:u1|bcd:u1|BCD4suber:us|Complementor:u3
}
# end
# entity
vga
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
vga.vhd
1147322183
4
# storage
db|Ivga.(9).cnf
db|Ivga.(9).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
VgaInterface:u2|vga:u1
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|Ivga.(10).cnf
db|Ivga.(10).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
1
PARAMETER_DEC
USR
WIDTHAD_A
16
PARAMETER_DEC
USR
NUMWORDS_A
65536
PARAMETER_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE
C:/Documents and Settings/wangjian/Desktop/VGA参考资料/VGA参考资料/PictureToCode工具及实例/example/picture.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_7mv
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a0
address_a10
address_a11
address_a12
address_a13
address_a14
address_a15
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
clock0
q_a0
}
# include_file {
..|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|libraries|megafunctions|lpm_mux.inc
1107574776
..|libraries|megafunctions|lpm_decode.inc
1107574570
..|libraries|megafunctions|aglobal50.inc
1118942284
..|libraries|megafunctions|altsyncram.inc
1107573506
..|libraries|megafunctions|a_rdenreg.inc
1107572148
..|libraries|megafunctions|altrom.inc
1107573422
..|libraries|megafunctions|altram.inc
1107573384
..|libraries|megafunctions|altdpram.inc
1107573082
..|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
VgaInterface:u2|vga:u1|altsyncram:altsyncram_component
}
# end
# entity
altsyncram_7mv
# case_insensitive
# source_file
db|altsyncram_7mv.tdf
1147322234
6
# storage
db|Ivga.(11).cnf
db|Ivga.(11).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
address_a13
address_a14
address_a15
clock0
q_a0
}
# memory_file {
C:|Documents and Settings|wangjian|Desktop|VGA参考资料|VGA参考资料|PictureToCode工具及实例|example|picture.mif
1147321828
}
# hierarchies {
VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated
}
# end
# entity
mux_gcb
# case_insensitive
# source_file
db|mux_gcb.tdf
1147322234
6
# storage
db|Ivga.(12).cnf
db|Ivga.(12).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
sel0
sel1
sel2
sel3
result0
}
# hierarchies {
VgaInterface:u2|vga:u1|altsyncram:altsyncram_component|altsyncram_7mv:auto_generated|mux_gcb:mux2
}
# end
# entity
VgaInterface
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
vgainterface.vhd
1147324631
4
# storage
db|Ivga.(8).cnf
db|Ivga.(8).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
VgaInterface:u2
}
# end
# complete