ivga.tan.qmsg

来自「用VHDL写的计算器」· QMSG 代码 · 共 13 行 · 第 1/4 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 11 13:23:53 2006 " "Info: Processing started: Thu May 11 13:23:53 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Ivga -c Ivga --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Ivga -c Ivga --timing_analysis_only" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_vga " "Info: Assuming node \"clk_vga\" is an undefined clock" {  } { { "Ivga.vhd" "" { Text "E:/altera/quartus50/Ivga/Ivga.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk_vga" } } } }  } 0}  } {  } 0}